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aarch64: Add support for FEAT_B16B16 instructions. 

Hi,

This patch add support for SVE2.1 and SME2.1 non-widening BFloat16
(FEAT_B16B16) instructions.

Following instructions predicated, unpredicated and indexed
variants are added in this patch.

bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm,
bfmla,bfmls,bfmul and bfsub.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.
binutils-2_42-branch
Srinath Parvathaneni 3 years ago
committed by Nick Clifton
parent
5186cf88ac
commit
7e8d2d8757
7 changed files with 353 additions and 0 deletions
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  1. 1
      gas/config/tc-aarch64.c
  2. 106
      gas/testsuite/gas/aarch64/bfloat16-1.d
  3. 112
      gas/testsuite/gas/aarch64/bfloat16-1.s
  4. 4
      gas/testsuite/gas/aarch64/bfloat16-bad.d
  5. 97
      gas/testsuite/gas/aarch64/bfloat16-bad.l
  6. 2
      include/opcode/aarch64.h
  7. 31
      opcodes/aarch64-tbl.h

1
gas/config/tc-aarch64.c
View File

@ -10335,6 +10335,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
{"d128", AARCH64_FEATURE (D128),
AARCH64_FEATURE (LSE128)},
{"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};

106
gas/testsuite/gas/aarch64/bfloat16-1.d
View File

@ -0,0 +1,106 @@
#name: Test of SVE2.1 and SME2.1 non-widening BFloat16 instructions.
#as: -march=armv9.4-a+b16b16
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
.*: 65008200 bfadd z0.h, p0\/m, z0.h, z16.h
.*: 65008501 bfadd z1.h, p1\/m, z1.h, z8.h
.*: 65008882 bfadd z2.h, p2\/m, z2.h, z4.h
.*: 65009044 bfadd z4.h, p4\/m, z4.h, z2.h
.*: 65009828 bfadd z8.h, p6\/m, z8.h, z1.h
.*: 65009c10 bfadd z16.h, p7\/m, z16.h, z0.h
.*: 65068200 bfmax z0.h, p0\/m, z0.h, z16.h
.*: 65068501 bfmax z1.h, p1\/m, z1.h, z8.h
.*: 65068882 bfmax z2.h, p2\/m, z2.h, z4.h
.*: 65069044 bfmax z4.h, p4\/m, z4.h, z2.h
.*: 65069828 bfmax z8.h, p6\/m, z8.h, z1.h
.*: 65069c10 bfmax z16.h, p7\/m, z16.h, z0.h
.*: 65048200 bfmaxnm z0.h, p0\/m, z0.h, z16.h
.*: 65048501 bfmaxnm z1.h, p1\/m, z1.h, z8.h
.*: 65048882 bfmaxnm z2.h, p2\/m, z2.h, z4.h
.*: 65049044 bfmaxnm z4.h, p4\/m, z4.h, z2.h
.*: 65049828 bfmaxnm z8.h, p6\/m, z8.h, z1.h
.*: 65049c10 bfmaxnm z16.h, p7\/m, z16.h, z0.h
.*: 65078200 bfmin z0.h, p0\/m, z0.h, z16.h
.*: 65078501 bfmin z1.h, p1\/m, z1.h, z8.h
.*: 65078882 bfmin z2.h, p2\/m, z2.h, z4.h
.*: 65079044 bfmin z4.h, p4\/m, z4.h, z2.h
.*: 65079828 bfmin z8.h, p6\/m, z8.h, z1.h
.*: 65079c10 bfmin z16.h, p7\/m, z16.h, z0.h
.*: 65058200 bfminnm z0.h, p0\/m, z0.h, z16.h
.*: 65058501 bfminnm z1.h, p1\/m, z1.h, z8.h
.*: 65058882 bfminnm z2.h, p2\/m, z2.h, z4.h
.*: 65059044 bfminnm z4.h, p4\/m, z4.h, z2.h
.*: 65059828 bfminnm z8.h, p6\/m, z8.h, z1.h
.*: 65059c10 bfminnm z16.h, p7\/m, z16.h, z0.h
.*: 65100080 bfadd z0.h, z4.h, z16.h
.*: 65080101 bfadd z1.h, z8.h, z8.h
.*: 65040182 bfadd z2.h, z12.h, z4.h
.*: 65020204 bfadd z4.h, z16.h, z2.h
.*: 65010288 bfadd z8.h, z20.h, z1.h
.*: 65000310 bfadd z16.h, z24.h, z0.h
.*: 64302480 bfclamp z0.h, z4.h, z16.h
.*: 64282501 bfclamp z1.h, z8.h, z8.h
.*: 64242582 bfclamp z2.h, z12.h, z4.h
.*: 64222604 bfclamp z4.h, z16.h, z2.h
.*: 64212688 bfclamp z8.h, z20.h, z1.h
.*: 64202710 bfclamp z16.h, z24.h, z0.h
.*: 65300000 bfmla z0.h, p0\/m, z0.h, z16.h
.*: 65280421 bfmla z1.h, p1\/m, z1.h, z8.h
.*: 65240842 bfmla z2.h, p2\/m, z2.h, z4.h
.*: 65221084 bfmla z4.h, p4\/m, z4.h, z2.h
.*: 65211908 bfmla z8.h, p6\/m, z8.h, z1.h
.*: 65201e10 bfmla z16.h, p7\/m, z16.h, z0.h
.*: 643e0a00 bfmla z0.h, z16.h, z6.h\[7\]
.*: 643d0901 bfmla z1.h, z8.h, z5.h\[7\]
.*: 643409c2 bfmla z2.h, z14.h, z4.h\[5\]
.*: 642a0aa4 bfmla z4.h, z21.h, z2.h\[3\]
.*: 64210988 bfmla z8.h, z12.h, z1.h\[1\]
.*: 64200950 bfmla z16.h, z10.h, z0.h\[1\]
.*: 65302000 bfmls z0.h, p0\/m, z0.h, z16.h
.*: 65282421 bfmls z1.h, p1\/m, z1.h, z8.h
.*: 65242842 bfmls z2.h, p2\/m, z2.h, z4.h
.*: 65223084 bfmls z4.h, p4\/m, z4.h, z2.h
.*: 65213908 bfmls z8.h, p6\/m, z8.h, z1.h
.*: 65203e10 bfmls z16.h, p7\/m, z16.h, z0.h
.*: 643e0e00 bfmls z0.h, z16.h, z6.h\[7\]
.*: 643d0d01 bfmls z1.h, z8.h, z5.h\[7\]
.*: 64340dc2 bfmls z2.h, z14.h, z4.h\[5\]
.*: 642a0ea4 bfmls z4.h, z21.h, z2.h\[3\]
.*: 64210d88 bfmls z8.h, z12.h, z1.h\[1\]
.*: 64200d50 bfmls z16.h, z10.h, z0.h\[1\]
.*: 65028200 bfmul z0.h, p0\/m, z0.h, z16.h
.*: 65028501 bfmul z1.h, p1\/m, z1.h, z8.h
.*: 65028882 bfmul z2.h, p2\/m, z2.h, z4.h
.*: 65029044 bfmul z4.h, p4\/m, z4.h, z2.h
.*: 65029828 bfmul z8.h, p6\/m, z8.h, z1.h
.*: 65029c10 bfmul z16.h, p7\/m, z16.h, z0.h
.*: 65100880 bfmul z0.h, z4.h, z16.h
.*: 65080901 bfmul z1.h, z8.h, z8.h
.*: 65040982 bfmul z2.h, z12.h, z4.h
.*: 65020a04 bfmul z4.h, z16.h, z2.h
.*: 65010a88 bfmul z8.h, z20.h, z1.h
.*: 65000b10 bfmul z16.h, z24.h, z0.h
.*: 643e2a00 bfmul z0.h, z16.h, z6.h\[7\]
.*: 643d2901 bfmul z1.h, z8.h, z5.h\[7\]
.*: 643429c2 bfmul z2.h, z14.h, z4.h\[5\]
.*: 642a2aa4 bfmul z4.h, z21.h, z2.h\[3\]
.*: 64212988 bfmul z8.h, z12.h, z1.h\[1\]
.*: 64202950 bfmul z16.h, z10.h, z0.h\[1\]
.*: 65018200 bfsub z0.h, p0\/m, z0.h, z16.h
.*: 65018501 bfsub z1.h, p1\/m, z1.h, z8.h
.*: 65018882 bfsub z2.h, p2\/m, z2.h, z4.h
.*: 65019044 bfsub z4.h, p4\/m, z4.h, z2.h
.*: 65019828 bfsub z8.h, p6\/m, z8.h, z1.h
.*: 65019c10 bfsub z16.h, p7\/m, z16.h, z0.h
.*: 65100480 bfsub z0.h, z4.h, z16.h
.*: 65080501 bfsub z1.h, z8.h, z8.h
.*: 65040582 bfsub z2.h, z12.h, z4.h
.*: 65020604 bfsub z4.h, z16.h, z2.h
.*: 65010688 bfsub z8.h, z20.h, z1.h
.*: 65000710 bfsub z16.h, z24.h, z0.h

112
gas/testsuite/gas/aarch64/bfloat16-1.s
View File

@ -0,0 +1,112 @@
bfadd z0.h, p0/m, z0.h, z16.h
bfadd z1.h, p1/m, z1.h, z8.h
bfadd z2.h, p2/m, z2.h, z4.h
bfadd z4.h, p4/m, z4.h, z2.h
bfadd z8.h, p6/m, z8.h, z1.h
bfadd z16.h, p7/m, z16.h, z0.h
bfmax z0.h, p0/m, z0.h, z16.h
bfmax z1.h, p1/m, z1.h, z8.h
bfmax z2.h, p2/m, z2.h, z4.h
bfmax z4.h, p4/m, z4.h, z2.h
bfmax z8.h, p6/m, z8.h, z1.h
bfmax z16.h, p7/m, z16.h, z0.h
bfmaxnm z0.h, p0/m, z0.h, z16.h
bfmaxnm z1.h, p1/m, z1.h, z8.h
bfmaxnm z2.h, p2/m, z2.h, z4.h
bfmaxnm z4.h, p4/m, z4.h, z2.h
bfmaxnm z8.h, p6/m, z8.h, z1.h
bfmaxnm z16.h, p7/m, z16.h, z0.h
bfmin z0.h, p0/m, z0.h, z16.h
bfmin z1.h, p1/m, z1.h, z8.h
bfmin z2.h, p2/m, z2.h, z4.h
bfmin z4.h, p4/m, z4.h, z2.h
bfmin z8.h, p6/m, z8.h, z1.h
bfmin z16.h, p7/m, z16.h, z0.h
bfminnm z0.h, p0/m, z0.h, z16.h
bfminnm z1.h, p1/m, z1.h, z8.h
bfminnm z2.h, p2/m, z2.h, z4.h
bfminnm z4.h, p4/m, z4.h, z2.h
bfminnm z8.h, p6/m, z8.h, z1.h
bfminnm z16.h, p7/m, z16.h, z0.h
bfadd z0.h, z4.h, z16.h
bfadd z1.h, z8.h, z8.h
bfadd z2.h, z12.h, z4.h
bfadd z4.h, z16.h, z2.h
bfadd z8.h, z20.h, z1.h
bfadd z16.h, z24.h, z0.h
bfclamp z0.h, z4.h, z16.h
bfclamp z1.h, z8.h, z8.h
bfclamp z2.h, z12.h, z4.h
bfclamp z4.h, z16.h, z2.h
bfclamp z8.h, z20.h, z1.h
bfclamp z16.h, z24.h, z0.h
bfmla z0.h, p0/m, z0.h, z16.h
bfmla z1.h, p1/m, z1.h, z8.h
bfmla z2.h, p2/m, z2.h, z4.h
bfmla z4.h, p4/m, z4.h, z2.h
bfmla z8.h, p6/m, z8.h, z1.h
bfmla z16.h, p7/m, z16.h, z0.h
bfmla z0.h, z16.h, z6.h[7]
bfmla z1.h, z8.h, z5.h[6]
bfmla z2.h, z14.h, z4.h[4]
bfmla z4.h, z21.h, z2.h[2]
bfmla z8.h, z12.h, z1.h[1]
bfmla z16.h, z10.h, z0.h[0]
bfmls z0.h, p0/m, z0.h, z16.h
bfmls z1.h, p1/m, z1.h, z8.h
bfmls z2.h, p2/m, z2.h, z4.h
bfmls z4.h, p4/m, z4.h, z2.h
bfmls z8.h, p6/m, z8.h, z1.h
bfmls z16.h, p7/m, z16.h, z0.h
bfmls z0.h, z16.h, z6.h[7]
bfmls z1.h, z8.h, z5.h[6]
bfmls z2.h, z14.h, z4.h[4]
bfmls z4.h, z21.h, z2.h[2]
bfmls z8.h, z12.h, z1.h[1]
bfmls z16.h, z10.h, z0.h[0]
bfmul z0.h, p0/m, z0.h, z16.h
bfmul z1.h, p1/m, z1.h, z8.h
bfmul z2.h, p2/m, z2.h, z4.h
bfmul z4.h, p4/m, z4.h, z2.h
bfmul z8.h, p6/m, z8.h, z1.h
bfmul z16.h, p7/m, z16.h, z0.h
bfmul z0.h, z4.h, z16.h
bfmul z1.h, z8.h, z8.h
bfmul z2.h, z12.h, z4.h
bfmul z4.h, z16.h, z2.h
bfmul z8.h, z20.h, z1.h
bfmul z16.h, z24.h, z0.h
bfmul z0.h, z16.h, z6.h[7]
bfmul z1.h, z8.h, z5.h[6]
bfmul z2.h, z14.h, z4.h[4]
bfmul z4.h, z21.h, z2.h[2]
bfmul z8.h, z12.h, z1.h[1]
bfmul z16.h, z10.h, z0.h[0]
bfsub z0.h, p0/m, z0.h, z16.h
bfsub z1.h, p1/m, z1.h, z8.h
bfsub z2.h, p2/m, z2.h, z4.h
bfsub z4.h, p4/m, z4.h, z2.h
bfsub z8.h, p6/m, z8.h, z1.h
bfsub z16.h, p7/m, z16.h, z0.h
bfsub z0.h, z4.h, z16.h
bfsub z1.h, z8.h, z8.h
bfsub z2.h, z12.h, z4.h
bfsub z4.h, z16.h, z2.h
bfsub z8.h, z20.h, z1.h
bfsub z16.h, z24.h, z0.h

4
gas/testsuite/gas/aarch64/bfloat16-bad.d
View File

@ -0,0 +1,4 @@
#name: Negative test of Bfloat16 instructions.
#as: -march=armv9.4-a
#source: bfloat16-1.s
#error_output: bfloat16-bad.l

97
gas/testsuite/gas/aarch64/bfloat16-bad.l
View File

@ -0,0 +1,97 @@
.*: Assembler messages:
.*: Error: selected processor does not support `bfadd z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfadd z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfadd z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfadd z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfadd z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfadd z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfmax z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfmax z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfmax z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfmax z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfmax z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfmax z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfmaxnm z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfmaxnm z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfmaxnm z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfmaxnm z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfmaxnm z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfmaxnm z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfmin z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfmin z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfmin z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfmin z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfmin z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfmin z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfminnm z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfminnm z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfminnm z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfminnm z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfminnm z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfminnm z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfadd z0.h,z4.h,z16.h'
.*: Error: selected processor does not support `bfadd z1.h,z8.h,z8.h'
.*: Error: selected processor does not support `bfadd z2.h,z12.h,z4.h'
.*: Error: selected processor does not support `bfadd z4.h,z16.h,z2.h'
.*: Error: selected processor does not support `bfadd z8.h,z20.h,z1.h'
.*: Error: selected processor does not support `bfadd z16.h,z24.h,z0.h'
.*: Error: selected processor does not support `bfclamp z0.h,z4.h,z16.h'
.*: Error: selected processor does not support `bfclamp z1.h,z8.h,z8.h'
.*: Error: selected processor does not support `bfclamp z2.h,z12.h,z4.h'
.*: Error: selected processor does not support `bfclamp z4.h,z16.h,z2.h'
.*: Error: selected processor does not support `bfclamp z8.h,z20.h,z1.h'
.*: Error: selected processor does not support `bfclamp z16.h,z24.h,z0.h'
.*: Error: selected processor does not support `bfmla z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfmla z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfmla z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfmla z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfmla z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfmla z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfmla z0.h,z16.h,z6.h\[7\]'
.*: Error: selected processor does not support `bfmla z1.h,z8.h,z5.h\[6\]'
.*: Error: selected processor does not support `bfmla z2.h,z14.h,z4.h\[4\]'
.*: Error: selected processor does not support `bfmla z4.h,z21.h,z2.h\[2\]'
.*: Error: selected processor does not support `bfmla z8.h,z12.h,z1.h\[1\]'
.*: Error: selected processor does not support `bfmla z16.h,z10.h,z0.h\[0\]'
.*: Error: selected processor does not support `bfmls z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfmls z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfmls z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfmls z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfmls z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfmls z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfmls z0.h,z16.h,z6.h\[7\]'
.*: Error: selected processor does not support `bfmls z1.h,z8.h,z5.h\[6\]'
.*: Error: selected processor does not support `bfmls z2.h,z14.h,z4.h\[4\]'
.*: Error: selected processor does not support `bfmls z4.h,z21.h,z2.h\[2\]'
.*: Error: selected processor does not support `bfmls z8.h,z12.h,z1.h\[1\]'
.*: Error: selected processor does not support `bfmls z16.h,z10.h,z0.h\[0\]'
.*: Error: selected processor does not support `bfmul z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfmul z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfmul z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfmul z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfmul z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfmul z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfmul z0.h,z4.h,z16.h'
.*: Error: selected processor does not support `bfmul z1.h,z8.h,z8.h'
.*: Error: selected processor does not support `bfmul z2.h,z12.h,z4.h'
.*: Error: selected processor does not support `bfmul z4.h,z16.h,z2.h'
.*: Error: selected processor does not support `bfmul z8.h,z20.h,z1.h'
.*: Error: selected processor does not support `bfmul z16.h,z24.h,z0.h'
.*: Error: selected processor does not support `bfmul z0.h,z16.h,z6.h\[7\]'
.*: Error: selected processor does not support `bfmul z1.h,z8.h,z5.h\[6\]'
.*: Error: selected processor does not support `bfmul z2.h,z14.h,z4.h\[4\]'
.*: Error: selected processor does not support `bfmul z4.h,z21.h,z2.h\[2\]'
.*: Error: selected processor does not support `bfmul z8.h,z12.h,z1.h\[1\]'
.*: Error: selected processor does not support `bfmul z16.h,z10.h,z0.h\[0\]'
.*: Error: selected processor does not support `bfsub z0.h,p0\/m,z0.h,z16.h'
.*: Error: selected processor does not support `bfsub z1.h,p1\/m,z1.h,z8.h'
.*: Error: selected processor does not support `bfsub z2.h,p2\/m,z2.h,z4.h'
.*: Error: selected processor does not support `bfsub z4.h,p4\/m,z4.h,z2.h'
.*: Error: selected processor does not support `bfsub z8.h,p6\/m,z8.h,z1.h'
.*: Error: selected processor does not support `bfsub z16.h,p7\/m,z16.h,z0.h'
.*: Error: selected processor does not support `bfsub z0.h,z4.h,z16.h'
.*: Error: selected processor does not support `bfsub z1.h,z8.h,z8.h'
.*: Error: selected processor does not support `bfsub z2.h,z12.h,z4.h'
.*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
.*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
.*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'

2
include/opcode/aarch64.h
View File

@ -222,6 +222,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PMUv3_ICNTR,
/* Performance Monitors Synchronous-Exception-Based Event Extension. */
AARCH64_FEATURE_SEBEP,
/* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
AARCH64_FEATURE_B16B16,
AARCH64_NUM_FEATURES
};

31
opcodes/aarch64-tbl.h
View File

@ -1761,6 +1761,10 @@
{ \
QLF3(S_S,NIL,S_S), \
}
#define OP_SVE_SMSS \
{ \
QLF4(S_H,P_M,S_H,S_H), \
}
#define OP_SVE_SUU \
{ \
QLF3(S_S,NIL,NIL), \
@ -2608,6 +2612,8 @@ static const aarch64_feature_set aarch64_feature_the =
AARCH64_FEATURE (THE);
static const aarch64_feature_set aarch64_feature_d128_the =
AARCH64_FEATURES (2, D128, THE);
static const aarch64_feature_set aarch64_feature_b16b16 =
AARCH64_FEATURE (B16B16);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@ -2670,6 +2676,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define D128 &aarch64_feature_d128
#define THE &aarch64_feature_the
#define D128_THE &aarch64_feature_d128_the
#define B16B16 &aarch64_feature_b16b16
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -2739,6 +2746,12 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@ -6258,6 +6271,24 @@ const struct aarch64_opcode aarch64_opcode_table[] =
D128_THE_INSN("rcwsswppal", 0x59e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
/* BFloat16 SVE Instructions. */
B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};

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