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MIPS/GAS: Implement microMIPS branch/jump compaction 

Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.

Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous.  This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has.  Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.

Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form.  For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction.  A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.

Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well.  We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded.  Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.

For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.

	gas/
	* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
	(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
	(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
	(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
	(get_append_method): Also return APPEND_ADD_COMPACT for
	microMIPS instructions.
	(find_altered_mips16_opcode): Exclude macros from matching.
	Factor code out...
	(find_altered_opcode): ... to this new function.
	(find_altered_micromips_opcode): New function.
	(frag_branch_delay_slot_size): Likewise.
	(append_insn): Handle microMIPS branch/jump compaction.
	(macro_start): Likewise.
	(relaxed_micromips_32bit_branch_length): Likewise.
	(md_convert_frag): Likewise.
	* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
	for delay slot filling.
	* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
	delay slot filling.
	* testsuite/gas/mips/micromips-size-1.s: Likewise.
	* testsuite/gas/mips/micromips.l: Adjust line numbers.
	* testsuite/gas/mips/micromips-warn.l: Likewise.
	* testsuite/gas/mips/micromips-size-1.l: Likewise.
	* testsuite/gas/mips/micromips.d: Adjust padding.
	* testsuite/gas/mips/micromips-trap.d: Likewise.
	* testsuite/gas/mips/micromips-insn32.d: Likewise.
	* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* testsuite/gas/mips/micromips@beq.d: Update patterns for
	branch/jump compaction.
	* testsuite/gas/mips/micromips@bge.d: Likewise.
	* testsuite/gas/mips/micromips@bgeu.d: Likewise.
	* testsuite/gas/mips/micromips@blt.d: Likewise.
	* testsuite/gas/mips/micromips@bltu.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
	* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
	* testsuite/gas/mips/micromips@relax.d: Likewise.
	* testsuite/gas/mips/micromips@relax-at.d: Likewise.
	* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
	* testsuite/gas/mips/branch-extern-2.d: Likewise.
	* testsuite/gas/mips/branch-extern-4.d: Likewise.
	* testsuite/gas/mips/branch-section-2.d: Likewise.
	* testsuite/gas/mips/branch-section-4.d: Likewise.
	* testsuite/gas/mips/branch-weak-2.d: Likewise.
	* testsuite/gas/mips/branch-weak-5.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips-compact.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.

	ld/
	* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
	patterns for branch compaction.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
	Likewise.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
	"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
	"j".
users/ARM/sve
Maciej W. Rozycki 10 years ago
parent
db18dbabad
commit
7bd374a44d
50 changed files with 8579 additions and 663 deletions
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  1. 70
      gas/ChangeLog
  2. 254
      gas/config/tc-mips.c
  3. 3
      gas/testsuite/gas/mips/branch-extern-2.d
  4. 3
      gas/testsuite/gas/mips/branch-extern-4.d
  5. 6
      gas/testsuite/gas/mips/branch-section-2.d
  6. 3
      gas/testsuite/gas/mips/branch-section-4.d
  7. 3
      gas/testsuite/gas/mips/branch-weak-2.d
  8. 3
      gas/testsuite/gas/mips/branch-weak-5.d
  9. 6
      gas/testsuite/gas/mips/micromips-b16.s
  10. 13
      gas/testsuite/gas/mips/micromips-branch-absolute-addend-n32.d
  11. 13
      gas/testsuite/gas/mips/micromips-branch-absolute-addend-n64.d
  12. 13
      gas/testsuite/gas/mips/micromips-branch-absolute-addend.d
  13. 13
      gas/testsuite/gas/mips/micromips-branch-absolute-n32.d
  14. 13
      gas/testsuite/gas/mips/micromips-branch-absolute-n64.d
  15. 13
      gas/testsuite/gas/mips/micromips-branch-absolute.d
  16. 7710
      gas/testsuite/gas/mips/micromips-compact.d
  17. 2
      gas/testsuite/gas/mips/micromips-insn32.d
  18. 2
      gas/testsuite/gas/mips/micromips-noinsn32.d
  19. 14
      gas/testsuite/gas/mips/micromips-size-1.l
  20. 8
      gas/testsuite/gas/mips/micromips-size-1.s
  21. 2
      gas/testsuite/gas/mips/micromips-trap.d
  22. 52
      gas/testsuite/gas/mips/micromips-warn.l
  23. 2
      gas/testsuite/gas/mips/micromips.d
  24. 212
      gas/testsuite/gas/mips/micromips.l
  25. 91
      gas/testsuite/gas/mips/micromips.s
  26. 44
      gas/testsuite/gas/mips/micromips@beq.d
  27. 70
      gas/testsuite/gas/mips/micromips@bge.d
  28. 64
      gas/testsuite/gas/mips/micromips@bgeu.d
  29. 70
      gas/testsuite/gas/mips/micromips@blt.d
  30. 64
      gas/testsuite/gas/mips/micromips@bltu.d
  31. 12
      gas/testsuite/gas/mips/micromips@branch-misc-4-64.d
  32. 12
      gas/testsuite/gas/mips/micromips@branch-misc-4.d
  33. 22
      gas/testsuite/gas/mips/micromips@branch-misc-5-64.d
  34. 14
      gas/testsuite/gas/mips/micromips@branch-misc-5.d
  35. 22
      gas/testsuite/gas/mips/micromips@branch-misc-5pic-64.d
  36. 14
      gas/testsuite/gas/mips/micromips@branch-misc-5pic.d
  37. 3
      gas/testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d
  38. 3
      gas/testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d
  39. 3
      gas/testsuite/gas/mips/micromips@jal-svr4pic-local.d
  40. 6
      gas/testsuite/gas/mips/micromips@loc-swap-dis.d
  41. 30
      gas/testsuite/gas/mips/micromips@loc-swap.d
  42. 98
      gas/testsuite/gas/mips/micromips@relax-at.d
  43. 7
      gas/testsuite/gas/mips/micromips@relax-swap3.d
  44. 98
      gas/testsuite/gas/mips/micromips@relax.d
  45. 1
      gas/testsuite/gas/mips/mips.exp
  46. 7
      ld/ChangeLog
  47. 13
      ld/testsuite/ld-mips-elf/micromips-branch-absolute-addend.d
  48. 13
      ld/testsuite/ld-mips-elf/micromips-branch-absolute.d
  49. 6
      opcodes/ChangeLog
  50. 22
      opcodes/micromips-opc.c

70
gas/ChangeLog
View File

@ -1,3 +1,73 @@
2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
2016-07-27 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c: Add new global arc_addrtype_hash.

254
gas/config/tc-mips.c
View File

@ -1153,13 +1153,14 @@ static int mips_relax_branch;
code found in the opcode file for this relocation, the register
selected as the assembler temporary, whether in the 32-bit
instruction mode, whether the branch is unconditional, whether it is
compact, whether it stores the link address implicitly in $ra,
whether relaxation of out-of-range 32-bit branches to a sequence of
compact, whether there is no delay-slot instruction available to fill
in, whether it stores the link address implicitly in $ra, whether
relaxation of out-of-range 32-bit branches to a sequence of
instructions is enabled, and whether the displacement of a branch is
too large to fit as an immediate argument of a 16-bit and a 32-bit
branch, respectively. */
#define RELAX_MICROMIPS_ENCODE(type, at, insn32, \
uncond, compact, link, \
uncond, compact, link, nods, \
relax32, toofar16, toofar32) \
(0x40000000 \
| ((type) & 0xff) \
@ -1168,9 +1169,10 @@ static int mips_relax_branch;
| ((uncond) ? 0x4000 : 0) \
| ((compact) ? 0x8000 : 0) \
| ((link) ? 0x10000 : 0) \
| ((relax32) ? 0x20000 : 0) \
| ((toofar16) ? 0x40000 : 0) \
| ((toofar32) ? 0x80000 : 0))
| ((nods) ? 0x20000 : 0) \
| ((relax32) ? 0x40000 : 0) \
| ((toofar16) ? 0x80000 : 0) \
| ((toofar32) ? 0x100000 : 0))
#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
@ -1178,14 +1180,15 @@ static int mips_relax_branch;
#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
#define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x20000) != 0)
#define RELAX_MICROMIPS_NODS(i) (((i) & 0x20000) != 0)
#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x40000) != 0)
#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x40000) != 0)
#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x40000)
#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x40000)
#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x80000) != 0)
#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x80000)
#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x80000)
#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x80000) != 0)
#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x80000)
#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x80000)
#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x100000) != 0)
#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x100000)
#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x100000)
/* Sign-extend 16-bit value X. */
#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
@ -6830,23 +6833,33 @@ get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
&& gpr_read_mask (ip) != 0)
return APPEND_ADD_COMPACT;
if (mips_opts.micromips
&& ((ip->insn_opcode & 0xffe0) == 0x4580
|| (!forced_insn_length
&& ((ip->insn_opcode & 0xfc00) == 0xcc00
|| (ip->insn_opcode & 0xdc00) == 0x8c00))
|| (ip->insn_opcode & 0xdfe00000) == 0x94000000
|| (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
return APPEND_ADD_COMPACT;
return APPEND_ADD_WITH_NOP;
}
return APPEND_ADD;
}
/* IP is a MIPS16 instruction whose opcode we have just changed.
Point IP->insn_mo to the new opcode's definition. */
/* IP is an instruction whose opcode we have just changed, END points
to the end of the opcode table processed. Point IP->insn_mo to the
new opcode's definition. */
static void
find_altered_mips16_opcode (struct mips_cl_insn *ip)
find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
{
const struct mips_opcode *mo, *end;
const struct mips_opcode *mo;
end = &mips16_opcodes[bfd_mips16_num_opcodes];
for (mo = ip->insn_mo; mo < end; mo++)
if ((ip->insn_opcode & mo->mask) == mo->match)
if (mo->pinfo != INSN_MACRO
&& (ip->insn_opcode & mo->mask) == mo->match)
{
ip->insn_mo = mo;
return;
@ -6854,6 +6867,24 @@ find_altered_mips16_opcode (struct mips_cl_insn *ip)
abort ();
}
/* IP is a MIPS16 instruction whose opcode we have just changed.
Point IP->insn_mo to the new opcode's definition. */
static void
find_altered_mips16_opcode (struct mips_cl_insn *ip)
{
find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
}
/* IP is a microMIPS instruction whose opcode we have just changed.
Point IP->insn_mo to the new opcode's definition. */
static void
find_altered_micromips_opcode (struct mips_cl_insn *ip)
{
find_altered_opcode (ip, &micromips_opcodes[bfd_micromips_num_opcodes]);
}
/* For microMIPS macros, we need to generate a local number label
as the target of branches. */
#define MICROMIPS_LABEL_CHAR '\037'
@ -7042,8 +7073,14 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
prev_pinfo2 = history[0].insn_mo->pinfo2;
pinfo = ip->insn_mo->pinfo;
/* Don't raise alarm about `nods' frags as they'll fill in the right
kind of nop in relaxation if required. */
if (mips_opts.micromips
&& !expansionp
&& !(history[0].frag
&& history[0].frag->fr_type == rs_machine_dependent
&& RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
&& RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
&& (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
&& micromips_insn_length (ip->insn_mo) != 2)
|| ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
@ -7293,21 +7330,26 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
16-bit/32-bit instructions. */
&& !forced_insn_length)
{
bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
&& *reloc_type > BFD_RELOC_UNUSED);
int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
int uncond = uncond_branch_p (ip) ? -1 : 0;
int compact = compact_branch_p (ip);
int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
int nods = method == APPEND_ADD_WITH_NOP;
int al = pinfo & INSN_WRITE_GPR_31;
int length32;
int length32 = nods ? 8 : 4;
gas_assert (address_expr != NULL);
gas_assert (!mips_relax.sequence);
relaxed_branch = TRUE;
length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
if (nods)
method = APPEND_ADD;
if (relax32)
length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
uncond, compact, al,
uncond, compact, al, nods,
relax32, 0, 0),
address_expr->X_add_symbol,
address_expr->X_add_number);
@ -7512,9 +7554,50 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
case APPEND_ADD_COMPACT:
/* Convert MIPS16 jr/jalr into a "compact" jump. */
gas_assert (mips_opts.mips16);
ip->insn_opcode |= 0x0080;
find_altered_mips16_opcode (ip);
if (mips_opts.mips16)
{
ip->insn_opcode |= 0x0080;
find_altered_mips16_opcode (ip);
}
/* Convert microMIPS instructions. */
else if (mips_opts.micromips)
{
/* jr16->jrc */
if ((ip->insn_opcode & 0xffe0) == 0x4580)
ip->insn_opcode |= 0x0020;
/* b16->bc */
else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
ip->insn_opcode = 0x40e00000;
/* beqz16->beqzc, bnez16->bnezc */
else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
{
unsigned long regno;
regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
regno &= MICROMIPSOP_MASK_MD;
regno = micromips_to_32_reg_d_map[regno];
ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
| (regno << MICROMIPSOP_SH_RS)
| 0x40a00000) ^ 0x00400000;
}
/* beqz->beqzc, bnez->bnezc */
else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
| ((ip->insn_opcode >> 7) & 0x00400000)
| 0x40a00000) ^ 0x00400000;
/* beq $0->beqzc, bne $0->bnezc */
else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
ip->insn_opcode = (((ip->insn_opcode >>
(MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
& (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
| ((ip->insn_opcode >> 7) & 0x00400000)
| 0x40a00000) ^ 0x00400000;
else
abort ();
find_altered_micromips_opcode (ip);
}
else
abort ();
install_insn (ip);
insert_into_history (0, 1, ip);
break;
@ -8274,19 +8357,25 @@ macro_start (void)
memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
mips_macro_warning.delay_slot_p = (mips_opts.noreorder
&& delayed_branch_p (&history[0]));
switch (history[0].insn_mo->pinfo2
& (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
{
case INSN2_BRANCH_DELAY_32BIT:
mips_macro_warning.delay_slot_length = 4;
break;
case INSN2_BRANCH_DELAY_16BIT:
mips_macro_warning.delay_slot_length = 2;
break;
default:
mips_macro_warning.delay_slot_length = 0;
break;
}
if (history[0].frag
&& history[0].frag->fr_type == rs_machine_dependent
&& RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
&& RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
mips_macro_warning.delay_slot_length = 0;
else
switch (history[0].insn_mo->pinfo2
& (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
{
case INSN2_BRANCH_DELAY_32BIT:
mips_macro_warning.delay_slot_length = 4;
break;
case INSN2_BRANCH_DELAY_16BIT:
mips_macro_warning.delay_slot_length = 2;
break;
default:
mips_macro_warning.delay_slot_length = 0;
break;
}
mips_macro_warning.first_frag = NULL;
}
@ -17185,6 +17274,21 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
return length;
}
/* Get a FRAG's branch instruction delay slot size, either from the
short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
or SHORT_INSN_SIZE otherwise. */
static int
frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
{
char *buf = fragp->fr_literal + fragp->fr_fix;
if (al)
return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
else
return short_insn_size;
}
/* Compute the length of a branch sequence, and adjust the
RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
worst-case length is computed, with UPDATE being used to indicate
@ -17194,9 +17298,21 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
static int
relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
{
bfd_boolean insn32 = TRUE;
bfd_boolean nods = TRUE;
bfd_boolean al = TRUE;
int short_insn_size;
bfd_boolean toofar;
int length;
if (fragp)
{
insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
}
short_insn_size = insn32 ? 4 : 2;
if (fragp
&& S_IS_DEFINED (fragp->fr_symbol)
&& !S_IS_WEAK (fragp->fr_symbol)
@ -17233,19 +17349,15 @@ relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
{
bfd_boolean compact_known = fragp != NULL;
bfd_boolean compact = FALSE;
bfd_boolean insn32 = TRUE;
bfd_boolean uncond;
int short_insn_size;
if (fragp)
{
compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
}
else
uncond = update < 0;
short_insn_size = insn32 ? 4 : 2;
/* If label is out of range, we turn branch <br>:
@ -17275,6 +17387,13 @@ relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
if (mips_pic != NO_PIC)
length += 4 + short_insn_size;
/* Add an extra nop if the jump has no compact form and we need
to fill the delay slot. */
if ((mips_pic == NO_PIC || al) && nods)
length += (fragp
? frag_branch_delay_slot_size (fragp, al, short_insn_size)
: short_insn_size);
/* If branch <br> is conditional, we prepend negated branch <brneg>:
<brneg> 0f # 4 bytes
@ -17283,6 +17402,12 @@ relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
if (!uncond)
length += (compact_known && compact) ? 4 : 4 + short_insn_size;
}
else if (nods)
{
/* Add an extra nop to fill the delay slot. */
gas_assert (fragp);
length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
}
return length;
}
@ -17847,6 +17972,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
char *buf = fragp->fr_literal + fragp->fr_fix;
bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
bfd_boolean short_ds;
@ -17898,7 +18024,22 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
fixp->fx_line = fragp->fr_line;
if (type == 0)
return;
{
insn = read_compressed_insn (buf, 4);
buf += 4;
if (nods)
{
/* Check the short-delay-slot bit. */
if (!al || (insn & 0x02000000) != 0)
buf = write_compressed_insn (buf, 0x0c00, 2);
else
buf = write_compressed_insn (buf, 0x00000000, 4);
}
gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
return;
}
}
/* Relax 16-bit branches to 32-bit branches. */
@ -17925,6 +18066,8 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
|| !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
{
buf = write_compressed_insn (buf, insn, 4);
if (nods)
buf = write_compressed_insn (buf, 0x0c00, 2);
gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
return;
}
@ -17937,7 +18080,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
_("relaxed out-of-range branch into a jump"));
/* Set the short-delay-slot bit. */
short_ds = al && (insn & 0x02000000) != 0;
short_ds = !al || (insn & 0x02000000) != 0;
if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
{
@ -18007,7 +18150,8 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
if (mips_pic == NO_PIC)
{
unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
unsigned long jal = (short_ds || nods
? 0x74000000 : 0xf4000000); /* jal/s */
/* j/jal/jals <sym> R_MICROMIPS_26_S1 */
insn = al ? jal : 0xd4000000;
@ -18019,7 +18163,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
buf = write_compressed_insn (buf, insn, 4);
if (compact)
if (compact || nods)
{
/* nop */
if (insn32)
@ -18068,7 +18212,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
buf = write_compressed_insn (buf, insn, 4);
if (compact)
if (compact || nods)
/* nop */
buf = write_compressed_insn (buf, 0x00000000, 4);
}
@ -18076,12 +18220,20 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
{
/* jr/jrc/jalr/jalrs $at */
unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
insn = al ? jalr : jr;
insn |= at << MICROMIPSOP_SH_MJ;
buf = write_compressed_insn (buf, insn, 2);
if (al && nods)
{
/* nop */
if (short_ds)
buf = write_compressed_insn (buf, 0x0c00, 2);
else
buf = write_compressed_insn (buf, 0x00000000, 4);
}
}
}

3
gas/testsuite/gas/mips/branch-extern-2.d
View File

@ -6,7 +6,6 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 fffe b 00000000 <foo>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00000000 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

3
gas/testsuite/gas/mips/branch-extern-4.d
View File

@ -11,6 +11,5 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 bar
[0-9a-f]+ <[^>]*> 3021 0000 addiu at,at,0
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
\.\.\.

6
gas/testsuite/gas/mips/branch-section-2.d
View File

@ -6,12 +6,10 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 fffe b 00000000 <foo>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00000000 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.
Disassembly of section \.init:
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45bf jrc ra
\.\.\.

3
gas/testsuite/gas/mips/branch-section-4.d
View File

@ -13,6 +13,5 @@ Disassembly of section \.text:
\.\.\.
Disassembly of section \.init:
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45bf jrc ra
\.\.\.

3
gas/testsuite/gas/mips/branch-weak-2.d
View File

@ -6,9 +6,8 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 fffe b 00000000 <foo>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00000000 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop

3
gas/testsuite/gas/mips/branch-weak-5.d
View File

@ -6,9 +6,8 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 fffe b 00000000 <foo>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00000000 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop

6
gas/testsuite/gas/mips/micromips-b16.s
View File

@ -2,16 +2,22 @@
test1:
.space 65536
test2:
nop
b16 1f
1:
nop
bnez16 $2,1f
1:
nop
beqz16 $2,1f
1:
nop
b 1f
1:
nop
bnez $2,1f
1:
nop
beqz $2,1f
1:
nop

13
gas/testsuite/gas/mips/micromips-branch-absolute-addend-n32.d
View File

@ -7,20 +7,17 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0000 b 00001004 <foo\+0x4>
[0-9a-f]+ <[^>]*> 40e0 0000 bc 00001004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 0000 bal 0000100a <foo\+0xa>
[0-9a-f]+ <[^>]*> 4060 0000 bal 00001008 <foo\+0x8>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,00001012 <foo\+0x12>
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,00001010 <foo\+0x10>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 0000 beqz v0,0000101a <foo\+0x1a>
[0-9a-f]+ <[^>]*> 40e2 0000 beqzc v0,00001018 <foo\+0x18>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 0000 bnez v0,00001020 <foo\+0x20>
[0-9a-f]+ <[^>]*> 40a2 0000 bnezc v0,0000101c <foo\+0x1c>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

13
gas/testsuite/gas/mips/micromips-branch-absolute-addend-n64.d
View File

@ -7,30 +7,27 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0000 b 0000000000001004 <foo\+0x4>
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0000000000001004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 0000 bal 000000000000100a <foo\+0xa>
[0-9a-f]+ <[^>]*> 4060 0000 bal 0000000000001008 <foo\+0x8>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,0000000000001012 <foo\+0x12>
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,0000000000001010 <foo\+0x10>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 0000 beqz v0,000000000000101a <foo\+0x1a>
[0-9a-f]+ <[^>]*> 40e2 0000 beqzc v0,0000000000001018 <foo\+0x18>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 0000 bnez v0,0000000000001020 <foo\+0x20>
[0-9a-f]+ <[^>]*> 40a2 0000 bnezc v0,000000000000101c <foo\+0x1c>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x123468a9
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

13
gas/testsuite/gas/mips/micromips-branch-absolute-addend.d
View File

@ -6,20 +6,17 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0918 b 00002234 <foo\+0x1234>
[0-9a-f]+ <[^>]*> 40e0 0918 bc 00002234 <foo\+0x1234>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 0918 bal 0000223a <foo\+0x123a>
[0-9a-f]+ <[^>]*> 4060 0918 bal 00002238 <foo\+0x1238>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 0918 bltzal zero,00002242 <foo\+0x1242>
[0-9a-f]+ <[^>]*> 4020 0918 bltzal zero,00002240 <foo\+0x1240>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 0918 beqz v0,0000224a <foo\+0x124a>
[0-9a-f]+ <[^>]*> 40e2 0918 beqzc v0,00002248 <foo\+0x1248>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 0918 bnez v0,00002250 <foo\+0x1250>
[0-9a-f]+ <[^>]*> 40a2 0918 bnezc v0,0000224c <foo\+0x124c>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

13
gas/testsuite/gas/mips/micromips-branch-absolute-n32.d
View File

@ -7,20 +7,17 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0000 b 00001004 <foo\+0x4>
[0-9a-f]+ <[^>]*> 40e0 0000 bc 00001004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 0000 bal 0000100a <foo\+0xa>
[0-9a-f]+ <[^>]*> 4060 0000 bal 00001008 <foo\+0x8>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,00001012 <foo\+0x12>
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,00001010 <foo\+0x10>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 0000 beqz v0,0000101a <foo\+0x1a>
[0-9a-f]+ <[^>]*> 40e2 0000 beqzc v0,00001018 <foo\+0x18>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 0000 bnez v0,00001020 <foo\+0x20>
[0-9a-f]+ <[^>]*> 40a2 0000 bnezc v0,0000101c <foo\+0x1c>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

13
gas/testsuite/gas/mips/micromips-branch-absolute-n64.d
View File

@ -7,30 +7,27 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0000 b 0000000000001004 <foo\+0x4>
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0000000000001004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 0000 bal 000000000000100a <foo\+0xa>
[0-9a-f]+ <[^>]*> 4060 0000 bal 0000000000001008 <foo\+0x8>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,0000000000001012 <foo\+0x12>
[0-9a-f]+ <[^>]*> 4020 0000 bltzal zero,0000000000001010 <foo\+0x10>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 0000 beqz v0,000000000000101a <foo\+0x1a>
[0-9a-f]+ <[^>]*> 40e2 0000 beqzc v0,0000000000001018 <foo\+0x18>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 0000 bnez v0,0000000000001020 <foo\+0x20>
[0-9a-f]+ <[^>]*> 40a2 0000 bnezc v0,000000000000101c <foo\+0x1c>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x1231
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

13
gas/testsuite/gas/mips/micromips-branch-absolute.d
View File

@ -6,20 +6,17 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 fffe b 00001000 <foo>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00001000 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 fffe bal 00001006 <foo\+0x6>
[0-9a-f]+ <[^>]*> 4060 fffe bal 00001004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 fffe bltzal zero,0000100e <foo\+0xe>
[0-9a-f]+ <[^>]*> 4020 fffe bltzal zero,0000100c <foo\+0xc>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 fffe beqz v0,00001016 <foo\+0x16>
[0-9a-f]+ <[^>]*> 40e2 fffe beqzc v0,00001014 <foo\+0x14>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 fffe bnez v0,0000101c <foo\+0x1c>
[0-9a-f]+ <[^>]*> 40a2 fffe bnezc v0,00001018 <foo\+0x18>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

7710
gas/testsuite/gas/mips/micromips-compact.d
View File

File diff suppressed because it is too large

2
gas/testsuite/gas/mips/micromips-insn32.d
View File

@ -683,6 +683,7 @@ Disassembly of section \.text:
[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
[ 0-9a-f]+: 0000 0000 nop
[ 0-9a-f]+: 0000 0000 nop
[ 0-9a-f]+: b402 fffe bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test3
[ 0-9a-f]+: 0000 0000 nop
@ -5068,6 +5069,7 @@ Disassembly of section \.text:
[ 0-9a-f]+: 03ff 937c wait 0x3ff
[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
[ 0-9a-f]+: 0000 0000 nop
[0-9a-f]+ <fp_test>:
[ 0-9a-f]+: 5400 01a0 prefx 0x0,zero\(zero\)

2
gas/testsuite/gas/mips/micromips-noinsn32.d
View File

@ -683,6 +683,7 @@ Disassembly of section \.text:
[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
[ 0-9a-f]+: 0c00 nop
@ -5045,7 +5046,6 @@ Disassembly of section \.text:
[ 0-9a-f]+: 03ff 937c wait 0x3ff
[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 0000 0000 nop
[0-9a-f]+ <fp_test>:

14
gas/testsuite/gas/mips/micromips-size-1.l
View File

@ -1,10 +1,10 @@
.*: Assembler messages:
.*:50: Warning: wrong size instruction in a 32-bit branch delay slot
.*:58: Warning: wrong size instruction in a 16-bit branch delay slot
.*:64: Warning: wrong size instruction in a 16-bit branch delay slot
.*:58: Warning: wrong size instruction in a 32-bit branch delay slot
.*:66: Warning: wrong size instruction in a 16-bit branch delay slot
.*:68: Warning: wrong size instruction in a 32-bit branch delay slot
.*:70: Warning: wrong size instruction in a 32-bit branch delay slot
.*:82: Warning: wrong size instruction in a 32-bit branch delay slot
.*:72: Warning: wrong size instruction in a 16-bit branch delay slot
.*:74: Warning: wrong size instruction in a 16-bit branch delay slot
.*:76: Warning: wrong size instruction in a 32-bit branch delay slot
.*:78: Warning: wrong size instruction in a 32-bit branch delay slot
.*:90: Warning: wrong size instruction in a 32-bit branch delay slot
.*:92: Warning: wrong size instruction in a 32-bit branch delay slot
.*:98: Warning: wrong size instruction in a 32-bit branch delay slot
.*:100: Warning: wrong size instruction in a 32-bit branch delay slot

8
gas/testsuite/gas/mips/micromips-size-1.s
View File

@ -33,13 +33,21 @@ foo:
jalr32 $31,$25
jalr $30,$26
jalr32 $30,$26
nop
b bar
nop
b16 bar
nop
b32 bar
nop
beqz $7, bar
nop
beqz16 $7, bar
nop
beqz32 $7, bar
nop
beqz $27, bar
nop
beqz32 $27, bar
# Test branch delay slots.

2
gas/testsuite/gas/mips/micromips-trap.d
View File

@ -700,6 +700,7 @@ Disassembly of section \.text:
[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
[ 0-9a-f]+: 0c00 nop
@ -5052,7 +5053,6 @@ Disassembly of section \.text:
[ 0-9a-f]+: 03ff 937c wait 0x3ff
[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
[ 0-9a-f]+: 0c00 nop
[0-9a-f]+ <fp_test>:
[ 0-9a-f]+: 5400 01a0 prefx 0x0,zero\(zero\)

52
gas/testsuite/gas/mips/micromips-warn.l
View File

@ -1,27 +1,27 @@
.*: Assembler messages:
.*:578: Warning: divide by zero
.*:581: Warning: divide by zero
.*:594: Warning: divide by zero
.*:1559: Warning: divide by zero
.*:1562: Warning: divide by zero
.*:1575: Warning: divide by zero
.*:2622: Warning: branch bge is always true
.*:2625: Warning: branch bgeu is always true
.*:2634: Warning: branch bgeu is always true
.*:2709: Warning: branch ble is always true
.*:2724: Warning: branch bleu is always true
.*:2730: Warning: branch bleu is always true
.*:2733: Warning: branch bleu is always true
.*:2832: Warning: branch bgel is always true
.*:2835: Warning: branch bgeul is always true
.*:2844: Warning: branch bgeul is always true
.*:2919: Warning: branch blel is always true
.*:2934: Warning: branch bleul is always true
.*:2940: Warning: branch bleul is always true
.*:2943: Warning: branch bleul is always true
.*:4759: Warning: divide by zero
.*:4762: Warning: divide by zero
.*:4775: Warning: divide by zero
.*:5180: Warning: divide by zero
.*:5190: Warning: divide by zero
.*:5200: Warning: divide by zero
.*:649: Warning: divide by zero
.*:652: Warning: divide by zero
.*:665: Warning: divide by zero
.*:1649: Warning: divide by zero
.*:1652: Warning: divide by zero
.*:1665: Warning: divide by zero
.*:2712: Warning: branch bge is always true
.*:2715: Warning: branch bgeu is always true
.*:2724: Warning: branch bgeu is always true
.*:2799: Warning: branch ble is always true
.*:2814: Warning: branch bleu is always true
.*:2820: Warning: branch bleu is always true
.*:2823: Warning: branch bleu is always true
.*:2922: Warning: branch bgel is always true
.*:2925: Warning: branch bgeul is always true
.*:2934: Warning: branch bgeul is always true
.*:3009: Warning: branch blel is always true
.*:3024: Warning: branch bleul is always true
.*:3030: Warning: branch bleul is always true
.*:3033: Warning: branch bleul is always true
.*:4849: Warning: divide by zero
.*:4852: Warning: divide by zero
.*:4865: Warning: divide by zero
.*:5270: Warning: divide by zero
.*:5280: Warning: divide by zero
.*:5290: Warning: divide by zero

2
gas/testsuite/gas/mips/micromips.d
View File

@ -700,6 +700,7 @@ Disassembly of section \.text:
[ 0-9a-f]+: 9411 fffe beqz s1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: 0c00 nop
[ 0-9a-f]+: ad7f bnez v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
[ 0-9a-f]+: 0c00 nop
@ -5124,7 +5125,6 @@ Disassembly of section \.text:
[ 0-9a-f]+: 03ff 937c wait 0x3ff
[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
[ 0-9a-f]+: 0c00 nop
[0-9a-f]+ <fp_test>:
[ 0-9a-f]+: 5400 01a0 prefx 0x0,zero\(zero\)

212
gas/testsuite/gas/mips/micromips.l
View File

@ -1,107 +1,107 @@
.*: Assembler messages:
.*:39: Error: opcode not supported in the `insn32' mode `nop16'
.*:98: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22'
.*:99: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2'
.*:106: Error: opcode not supported in the `insn32' mode `b16 test'
.*:111: Error: opcode not supported in the `insn32' mode `b16 1f'
.*:117: Error: opcode not supported in the `insn32' mode `b16 1b'
.*:277: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
.*:315: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535'
.*:387: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2'
.*:475: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3'
.*:578: Warning: divide by zero
.*:581: Warning: divide by zero
.*:594: Warning: divide by zero
.*:1559: Warning: divide by zero
.*:1562: Warning: divide by zero
.*:1575: Warning: divide by zero
.*:2622: Warning: branch bge is always true
.*:2625: Warning: branch bgeu is always true
.*:2634: Warning: branch bgeu is always true
.*:2709: Warning: branch ble is always true
.*:2724: Warning: branch bleu is always true
.*:2730: Warning: branch bleu is always true
.*:2733: Warning: branch bleu is always true
.*:2832: Warning: branch bgel is always true
.*:2835: Warning: branch bgeul is always true
.*:2844: Warning: branch bgeul is always true
.*:2919: Warning: branch blel is always true
.*:2934: Warning: branch bleul is always true
.*:2940: Warning: branch bleul is always true
.*:2943: Warning: branch bleul is always true
.*:3010: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,0'
.*:3011: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,1<<2'
.*:3012: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,2<<2'
.*:3013: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,3<<2'
.*:3014: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,4<<2'
.*:3015: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,63<<2'
.*:3016: Error: opcode not supported in the `insn32' mode `addiur1sp \$3,63<<2'
.*:3017: Error: opcode not supported in the `insn32' mode `addiur1sp \$4,63<<2'
.*:3018: Error: opcode not supported in the `insn32' mode `addiur1sp \$5,63<<2'
.*:3019: Error: opcode not supported in the `insn32' mode `addiur1sp \$6,63<<2'
.*:3020: Error: opcode not supported in the `insn32' mode `addiur1sp \$7,63<<2'
.*:3021: Error: opcode not supported in the `insn32' mode `addiur1sp \$16,63<<2'
.*:3022: Error: opcode not supported in the `insn32' mode `addiur1sp \$17,63<<2'
.*:3024: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$2,-1'
.*:3025: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$3,-1'
.*:3026: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$4,-1'
.*:3027: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$5,-1'
.*:3028: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$6,-1'
.*:3029: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$7,-1'
.*:3030: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$16,-1'
.*:3031: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$17,-1'
.*:3032: Error: opcode not supported in the `insn32' mode `addiur2 \$3,\$17,-1'
.*:3033: Error: opcode not supported in the `insn32' mode `addiur2 \$4,\$17,-1'
.*:3034: Error: opcode not supported in the `insn32' mode `addiur2 \$5,\$17,-1'
.*:3035: Error: opcode not supported in the `insn32' mode `addiur2 \$6,\$17,-1'
.*:3036: Error: opcode not supported in the `insn32' mode `addiur2 \$7,\$17,-1'
.*:3037: Error: opcode not supported in the `insn32' mode `addiur2 \$16,\$17,-1'
.*:3038: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,-1'
.*:3039: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,1'
.*:3040: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,4'
.*:3041: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,8'
.*:3042: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,12'
.*:3043: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16'
.*:3044: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20'
.*:3045: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24'
.*:3047: Error: opcode not supported in the `insn32' mode `addiusp 2<<2'
.*:3048: Error: opcode not supported in the `insn32' mode `addiusp 3<<2'
.*:3049: Error: opcode not supported in the `insn32' mode `addiusp 254<<2'
.*:3050: Error: opcode not supported in the `insn32' mode `addiusp 255<<2'
.*:3051: Error: opcode not supported in the `insn32' mode `addiusp 256<<2'
.*:3052: Error: opcode not supported in the `insn32' mode `addiusp 257<<2'
.*:3053: Error: opcode not supported in the `insn32' mode `addiusp -3<<2'
.*:3054: Error: opcode not supported in the `insn32' mode `addiusp -4<<2'
.*:3055: Error: opcode not supported in the `insn32' mode `addiusp -255<<2'
.*:3056: Error: opcode not supported in the `insn32' mode `addiusp -256<<2'
.*:3057: Error: opcode not supported in the `insn32' mode `addiusp -257<<2'
.*:3058: Error: opcode not supported in the `insn32' mode `addiusp -258<<2'
.*:3060: Error: opcode not supported in the `insn32' mode `addius5 \$0,0'
.*:3061: Error: opcode not supported in the `insn32' mode `addius5 \$2,0'
.*:3062: Error: opcode not supported in the `insn32' mode `addius5 \$3,0'
.*:3063: Error: opcode not supported in the `insn32' mode `addius5 \$30,0'
.*:3064: Error: opcode not supported in the `insn32' mode `addius5 \$31,0'
.*:3065: Error: opcode not supported in the `insn32' mode `addius5 \$31,1'
.*:3066: Error: opcode not supported in the `insn32' mode `addius5 \$31,2'
.*:3067: Error: opcode not supported in the `insn32' mode `addius5 \$31,3'
.*:3068: Error: opcode not supported in the `insn32' mode `addius5 \$31,7'
.*:3069: Error: opcode not supported in the `insn32' mode `addius5 \$31,-6'
.*:3070: Error: opcode not supported in the `insn32' mode `addius5 \$31,-7'
.*:3071: Error: opcode not supported in the `insn32' mode `addius5 \$31,-8'
.*:4759: Warning: divide by zero
.*:4762: Warning: divide by zero
.*:4775: Warning: divide by zero
.*:5180: Warning: divide by zero
.*:5190: Warning: divide by zero
.*:5200: Warning: divide by zero
.*:5568: Error: opcode not supported in the `insn32' mode `jalr16 \$2'
.*:5572: Error: opcode not supported in the `insn32' mode `jr16 \$2'
.*:5579: Error: opcode not supported in the `insn32' mode `jals test_delay_slot'
.*:5580: Error: opcode not supported in the `insn32' mode `jalrs16 \$2'
.*:5581: Error: opcode not supported in the `insn32' mode `jalrs32 \$2'
.*:5582: Error: opcode not supported in the `insn32' mode `jrs \$2'
.*:5583: Error: opcode not supported in the `insn32' mode `jalrs\.hb \$2'
.*:5584: Error: opcode not supported in the `insn32' mode `jrs\.hb \$2'
.*:5665: Error: opcode not supported in the `insn32' mode `bals test_spec107'
.*:5667: Error: opcode not supported in the `insn32' mode `bgezals \$2,test_spec107'
.*:5669: Error: opcode not supported in the `insn32' mode `bltzals \$2,test_spec107'
.*:49: Error: opcode not supported in the `insn32' mode `nop16'
.*:108: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22'
.*:109: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2'
.*:116: Error: opcode not supported in the `insn32' mode `b16 test'
.*:123: Error: opcode not supported in the `insn32' mode `b16 1f'
.*:131: Error: opcode not supported in the `insn32' mode `b16 1b'
.*:292: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
.*:330: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535'
.*:426: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2'
.*:543: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3'
.*:649: Warning: divide by zero
.*:652: Warning: divide by zero
.*:665: Warning: divide by zero
.*:1649: Warning: divide by zero
.*:1652: Warning: divide by zero
.*:1665: Warning: divide by zero
.*:2712: Warning: branch bge is always true
.*:2715: Warning: branch bgeu is always true
.*:2724: Warning: branch bgeu is always true
.*:2799: Warning: branch ble is always true
.*:2814: Warning: branch bleu is always true
.*:2820: Warning: branch bleu is always true
.*:2823: Warning: branch bleu is always true
.*:2922: Warning: branch bgel is always true
.*:2925: Warning: branch bgeul is always true
.*:2934: Warning: branch bgeul is always true
.*:3009: Warning: branch blel is always true
.*:3024: Warning: branch bleul is always true
.*:3030: Warning: branch bleul is always true
.*:3033: Warning: branch bleul is always true
.*:3100: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,0'
.*:3101: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,1<<2'
.*:3102: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,2<<2'
.*:3103: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,3<<2'
.*:3104: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,4<<2'
.*:3105: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,63<<2'
.*:3106: Error: opcode not supported in the `insn32' mode `addiur1sp \$3,63<<2'
.*:3107: Error: opcode not supported in the `insn32' mode `addiur1sp \$4,63<<2'
.*:3108: Error: opcode not supported in the `insn32' mode `addiur1sp \$5,63<<2'
.*:3109: Error: opcode not supported in the `insn32' mode `addiur1sp \$6,63<<2'
.*:3110: Error: opcode not supported in the `insn32' mode `addiur1sp \$7,63<<2'
.*:3111: Error: opcode not supported in the `insn32' mode `addiur1sp \$16,63<<2'
.*:3112: Error: opcode not supported in the `insn32' mode `addiur1sp \$17,63<<2'
.*:3114: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$2,-1'
.*:3115: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$3,-1'
.*:3116: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$4,-1'
.*:3117: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$5,-1'
.*:3118: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$6,-1'
.*:3119: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$7,-1'
.*:3120: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$16,-1'
.*:3121: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$17,-1'
.*:3122: Error: opcode not supported in the `insn32' mode `addiur2 \$3,\$17,-1'
.*:3123: Error: opcode not supported in the `insn32' mode `addiur2 \$4,\$17,-1'
.*:3124: Error: opcode not supported in the `insn32' mode `addiur2 \$5,\$17,-1'
.*:3125: Error: opcode not supported in the `insn32' mode `addiur2 \$6,\$17,-1'
.*:3126: Error: opcode not supported in the `insn32' mode `addiur2 \$7,\$17,-1'
.*:3127: Error: opcode not supported in the `insn32' mode `addiur2 \$16,\$17,-1'
.*:3128: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,-1'
.*:3129: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,1'
.*:3130: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,4'
.*:3131: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,8'
.*:3132: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,12'
.*:3133: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16'
.*:3134: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20'
.*:3135: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24'
.*:3137: Error: opcode not supported in the `insn32' mode `addiusp 2<<2'
.*:3138: Error: opcode not supported in the `insn32' mode `addiusp 3<<2'
.*:3139: Error: opcode not supported in the `insn32' mode `addiusp 254<<2'
.*:3140: Error: opcode not supported in the `insn32' mode `addiusp 255<<2'
.*:3141: Error: opcode not supported in the `insn32' mode `addiusp 256<<2'
.*:3142: Error: opcode not supported in the `insn32' mode `addiusp 257<<2'
.*:3143: Error: opcode not supported in the `insn32' mode `addiusp -3<<2'
.*:3144: Error: opcode not supported in the `insn32' mode `addiusp -4<<2'
.*:3145: Error: opcode not supported in the `insn32' mode `addiusp -255<<2'
.*:3146: Error: opcode not supported in the `insn32' mode `addiusp -256<<2'
.*:3147: Error: opcode not supported in the `insn32' mode `addiusp -257<<2'
.*:3148: Error: opcode not supported in the `insn32' mode `addiusp -258<<2'
.*:3150: Error: opcode not supported in the `insn32' mode `addius5 \$0,0'
.*:3151: Error: opcode not supported in the `insn32' mode `addius5 \$2,0'
.*:3152: Error: opcode not supported in the `insn32' mode `addius5 \$3,0'
.*:3153: Error: opcode not supported in the `insn32' mode `addius5 \$30,0'
.*:3154: Error: opcode not supported in the `insn32' mode `addius5 \$31,0'
.*:3155: Error: opcode not supported in the `insn32' mode `addius5 \$31,1'
.*:3156: Error: opcode not supported in the `insn32' mode `addius5 \$31,2'
.*:3157: Error: opcode not supported in the `insn32' mode `addius5 \$31,3'
.*:3158: Error: opcode not supported in the `insn32' mode `addius5 \$31,7'
.*:3159: Error: opcode not supported in the `insn32' mode `addius5 \$31,-6'
.*:3160: Error: opcode not supported in the `insn32' mode `addius5 \$31,-7'
.*:3161: Error: opcode not supported in the `insn32' mode `addius5 \$31,-8'
.*:4849: Warning: divide by zero
.*:4852: Warning: divide by zero
.*:4865: Warning: divide by zero
.*:5270: Warning: divide by zero
.*:5280: Warning: divide by zero
.*:5290: Warning: divide by zero
.*:5658: Error: opcode not supported in the `insn32' mode `jalr16 \$2'
.*:5663: Error: opcode not supported in the `insn32' mode `jr16 \$2'
.*:5670: Error: opcode not supported in the `insn32' mode `jals test_delay_slot'
.*:5671: Error: opcode not supported in the `insn32' mode `jalrs16 \$2'
.*:5672: Error: opcode not supported in the `insn32' mode `jalrs32 \$2'
.*:5673: Error: opcode not supported in the `insn32' mode `jrs \$2'
.*:5674: Error: opcode not supported in the `insn32' mode `jalrs\.hb \$2'
.*:5675: Error: opcode not supported in the `insn32' mode `jrs\.hb \$2'
.*:5756: Error: opcode not supported in the `insn32' mode `bals test_spec107'
.*:5758: Error: opcode not supported in the `insn32' mode `bgezals \$2,test_spec107'
.*:5760: Error: opcode not supported in the `insn32' mode `bltzals \$2,test_spec107'

91
gas/testsuite/gas/mips/micromips.s
View File

@ -1,6 +1,16 @@
.text
.align 3
.set micromips
.ifdef compact
.macro DSNOP
.endm
.else
.macro DSNOP
nop
.endm
.endif
.ent test
.globl test
test:
@ -105,17 +115,22 @@ test:
.ifndef insn32
b16 test
.endif
DSNOP
b32 test
DSNOP
b 1f
.ifndef insn32
b16 1f
.endif
DSNOP
b32 1f
1:
DSNOP
b 1b
.ifndef insn32
b16 1b
.endif
DSNOP
b32 1b
abs $2, $3
@ -358,40 +373,68 @@ test:
test2:
DSNOP
beqz $2, test2
DSNOP
beqz $3, test2
DSNOP
beqz $4, test2
DSNOP
beqz $5, test2
DSNOP
beqz $6, test2
DSNOP
beqz $7, test2
DSNOP
beqz $16, test2
DSNOP
beqz $17, test2
DSNOP
beq $2, $0, test2
DSNOP
beq $3, $0, test2
DSNOP
beq $4, $0, test2
DSNOP
beq $5, $0, test2
DSNOP
beq $6, $0, test2
DSNOP
beq $7, $0, test2
DSNOP
beq $16, $0, test2
DSNOP
beq $17, $0, test2
DSNOP
beq $0, $2, test2
DSNOP
beq $0, $3, test2
DSNOP
beq $0, $4, test2
DSNOP
beq $0, $5, test2
DSNOP
beq $0, $6, test2
DSNOP
beq $0, $7, test2
DSNOP
beq $0, $16, test2
DSNOP
beq $0, $17, test2
.ifndef insn32
beqz16 $16, test2
.endif
DSNOP
beqz32 $16, test2
DSNOP
beqz $17, test2
DSNOP
beqz32 $17, test2
beqzc $17, test2
DSNOP
beq $16, 0, test2
beq $16, 10, test2
beq $16, 32767, test2
@ -446,36 +489,64 @@ test2:
beqzl $17, test2
DSNOP
DSNOP
bnez $2, test3
DSNOP
bnez $3, test3
DSNOP
bnez $4, test3
DSNOP
bnez $5, test3
DSNOP
bnez $6, test3
DSNOP
bnez $7, test3
DSNOP
bnez $16, test3
DSNOP
bnez $17, test3
DSNOP
bne $2, $0, test3
DSNOP
bne $3, $0, test3
DSNOP
bne $4, $0, test3
DSNOP
bne $5, $0, test3
DSNOP
bne $6, $0, test3
DSNOP
bne $7, $0, test3
DSNOP
bne $16, $0, test3
DSNOP
bne $17, $0, test3
DSNOP
bne $0, $2, test3
DSNOP
bne $0, $3, test3
DSNOP
bne $0, $4, test3
DSNOP
bne $0, $5, test3
DSNOP
bne $0, $6, test3
DSNOP
bne $0, $7, test3
DSNOP
bne $0, $16, test3
DSNOP
bne $0, $17, test3
.ifndef insn32
bnez16 $16, test3
.endif
DSNOP
bnez32 $16, test3
DSNOP
bnez $17, test2
DSNOP
bnez32 $17, test2
test3:
bnezc $17, test2
@ -616,14 +687,23 @@ test3:
ins $31, $30, 31, 1
jr $0
DSNOP
jr $2
DSNOP
jr $3
DSNOP
jr $4
DSNOP
jr $5
DSNOP
jr $6
DSNOP
jr $7
DSNOP
jr $8
DSNOP
jr $30
DSNOP
jr $31
jr32 $0
@ -659,15 +739,25 @@ test3:
jr.hb $30
jr.hb $31
DSNOP
j $0
DSNOP
j $2
DSNOP
j $3
DSNOP
j $4
DSNOP
j $5
DSNOP
j $6
DSNOP
j $7
DSNOP
j $8
DSNOP
j $30
DSNOP
j $31
jalr $31, $0
@ -5569,6 +5659,7 @@ test_delay_slot:
.endif
jalr32 $2
.ifndef insn32
DSNOP
jr16 $2
.endif
jr32 $2

44
gas/testsuite/gas/mips/micromips@beq.d
View File

@ -11,44 +11,40 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 94a4 fffe beq a0,a1,0+0000 <text_label>
0: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0006 <text_label\+0x6>
[0-9a-f]+ <[^>]*> 40e4 fffe beqzc a0,0+0006 <text_label\+0x6>
6: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 3020 0001 li at,1
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+0010 <text_label\+0x10>
10: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+000e <text_label\+0xe>
e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+001a <text_label\+0x1a>
1a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+0018 <text_label\+0x18>
18: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+0024 <text_label\+0x24>
24: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+0022 <text_label\+0x22>
22: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+002e <text_label\+0x2e>
2e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+002c <text_label\+0x2c>
2c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+003c <text_label\+0x3c>
3c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0042 <text_label\+0x42>
42: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9424 fffe beq a0,at,0+003a <text_label\+0x3a>
3a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a4 fffe bnezc a0,0+0040 <text_label\+0x40>
40: R_MICROMIPS_PC16_S1 text_label
\.\.\.
[0-9a-f]+ <[^>]*> 9400 fffe b 00020048 <text_label\+0x20048>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00020044 <text_label\+0x20044>
20044: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4060 fffe bal 00020048 <text_label\+0x20048>
20048: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 fffe bal 0002004e <text_label\+0x2004e>
2004e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9400 fffe b 00020056 <text_label\+0x20056>
20056: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 fffe bal 0002005c <text_label\+0x2005c>
2005c: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 40e0 fffe bc 00020050 <text_label\+0x20050>
20050: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 4060 fffe bal 00020054 <text_label\+0x20054>
20054: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0000 0000 nop
\.\.\.

70
gas/testsuite/gas/mips/micromips@bge.d
View File

@ -9,64 +9,56 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0004 <text_label\+0x4>
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0004 <text_label\+0x4>
4: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,0+0008 <text_label\+0x8>
8: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,0+000a <text_label\+0xa>
a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4085 fffe blez a1,0+000e <text_label\+0xe>
e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4085 fffe blez a1,0+0010 <text_label\+0x10>
10: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,0+0014 <text_label\+0x14>
14: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4044 fffe bgez a0,0+0016 <text_label\+0x16>
16: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+001c <text_label\+0x1c>
1c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+001a <text_label\+0x1a>
1a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9024 0002 slti at,a0,2
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0026 <text_label\+0x26>
26: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0024 <text_label\+0x24>
24: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0034 <text_label\+0x34>
34: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0030 <text_label\+0x30>
30: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9024 8000 slti at,a0,-32768
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+003e <text_label\+0x3e>
3e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0038 <text_label\+0x38>
38: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+004c <text_label\+0x4c>
4c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0044 <text_label\+0x44>
44: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+005e <text_label\+0x5e>
5e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0054 <text_label\+0x54>
54: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0068 <text_label\+0x68>
68: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+005c <text_label\+0x5c>
5c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+0060 <text_label\+0x60>
60: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+006e <text_label\+0x6e>
6e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4005 fffe bltz a1,0+0066 <text_label\+0x66>
66: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4005 fffe bltz a1,0+0074 <text_label\+0x74>
74: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+007a <text_label\+0x7a>
7a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40c4 fffe bgtz a0,0+006c <text_label\+0x6c>
6c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0084 <text_label\+0x84>
84: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0076 <text_label\+0x76>
76: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+008e <text_label\+0x8e>
8e: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+007e <text_label\+0x7e>
7e: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

64
gas/testsuite/gas/mips/micromips@bgeu.d
View File

@ -9,56 +9,42 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0004 <text_label\+0x4>
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0004 <text_label\+0x4>
4: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 94a0 fffe beq zero,a1,0+000a <text_label\+0xa>
a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0010 <text_label\+0x10>
10: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e5 fffe beqzc a1,0+0008 <text_label\+0x8>
8: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40a4 fffe bnezc a0,0+000c <text_label\+0xc>
c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> b024 0002 sltiu at,a0,2
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+001a <text_label\+0x1a>
1a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0014 <text_label\+0x14>
14: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0028 <text_label\+0x28>
28: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0020 <text_label\+0x20>
20: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> b024 8000 sltiu at,a0,-32768
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0032 <text_label\+0x32>
32: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0028 <text_label\+0x28>
28: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0040 <text_label\+0x40>
40: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0034 <text_label\+0x34>
34: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0052 <text_label\+0x52>
52: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0044 <text_label\+0x44>
44: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+005c <text_label\+0x5c>
5c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0062 <text_label\+0x62>
62: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b404 fffe bnez a0,0+0068 <text_label\+0x68>
68: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+004c <text_label\+0x4c>
4c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40a4 fffe bnezc a0,0+0050 <text_label\+0x50>
50: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40a4 fffe bnezc a0,0+0054 <text_label\+0x54>
54: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0072 <text_label\+0x72>
72: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+005c <text_label\+0x5c>
5c: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+007c <text_label\+0x7c>
7c: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0064 <text_label\+0x64>
64: R_MICROMIPS_PC16_S1 external_label
\.\.\.

70
gas/testsuite/gas/mips/micromips@blt.d
View File

@ -9,64 +9,56 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0004 <text_label\+0x4>
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0004 <text_label\+0x4>
4: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4004 fffe bltz a0,0+0008 <text_label\+0x8>
8: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4004 fffe bltz a0,0+000a <text_label\+0xa>
a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40c5 fffe bgtz a1,0+000e <text_label\+0xe>
e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40c5 fffe bgtz a1,0+0010 <text_label\+0x10>
10: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4004 fffe bltz a0,0+0014 <text_label\+0x14>
14: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4004 fffe bltz a0,0+0016 <text_label\+0x16>
16: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+001c <text_label\+0x1c>
1c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+001a <text_label\+0x1a>
1a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9024 0002 slti at,a0,2
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0026 <text_label\+0x26>
26: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0024 <text_label\+0x24>
24: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0034 <text_label\+0x34>
34: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0030 <text_label\+0x30>
30: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 9024 8000 slti at,a0,-32768
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+003e <text_label\+0x3e>
3e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0038 <text_label\+0x38>
38: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+004c <text_label\+0x4c>
4c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0044 <text_label\+0x44>
44: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
[0-9a-f]+ <[^>]*> 0024 0b50 slt at,a0,at
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+005e <text_label\+0x5e>
5e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0054 <text_label\+0x54>
54: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+0068 <text_label\+0x68>
68: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+005c <text_label\+0x5c>
5c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+0060 <text_label\+0x60>
60: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+006e <text_label\+0x6e>
6e: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4045 fffe bgez a1,0+0066 <text_label\+0x66>
66: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4045 fffe bgez a1,0+0074 <text_label\+0x74>
74: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+007a <text_label\+0x7a>
7a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 4084 fffe blez a0,0+006c <text_label\+0x6c>
6c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 00a4 0b50 slt at,a0,a1
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0084 <text_label\+0x84>
84: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0076 <text_label\+0x76>
76: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0085 0b50 slt at,a1,a0
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+008e <text_label\+0x8e>
8e: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+007e <text_label\+0x7e>
7e: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

64
gas/testsuite/gas/mips/micromips@bltu.d
View File

@ -9,56 +9,42 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0004 <text_label\+0x4>
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0004 <text_label\+0x4>
4: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b4a0 fffe bne zero,a1,0+000a <text_label\+0xa>
a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0010 <text_label\+0x10>
10: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a5 fffe bnezc a1,0+0008 <text_label\+0x8>
8: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40e4 fffe beqzc a0,0+000c <text_label\+0xc>
c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> b024 0002 sltiu at,a0,2
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+001a <text_label\+0x1a>
1a: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0014 <text_label\+0x14>
14: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0028 <text_label\+0x28>
28: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0020 <text_label\+0x20>
20: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> b024 8000 sltiu at,a0,-32768
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0032 <text_label\+0x32>
32: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0028 <text_label\+0x28>
28: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0040 <text_label\+0x40>
40: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0034 <text_label\+0x34>
34: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1
[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
[0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0052 <text_label\+0x52>
52: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+0044 <text_label\+0x44>
44: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+005c <text_label\+0x5c>
5c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0062 <text_label\+0x62>
62: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9404 fffe beqz a0,0+0068 <text_label\+0x68>
68: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+004c <text_label\+0x4c>
4c: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40e4 fffe beqzc a0,0+0050 <text_label\+0x50>
50: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 40e4 fffe beqzc a0,0+0054 <text_label\+0x54>
54: R_MICROMIPS_PC16_S1 text_label
[0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
[0-9a-f]+ <[^>]*> b401 fffe bnez at,0+0072 <text_label\+0x72>
72: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40a1 fffe bnezc at,0+005c <text_label\+0x5c>
5c: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
[0-9a-f]+ <[^>]*> 9401 fffe beqz at,0+007c <text_label\+0x7c>
7c: R_MICROMIPS_PC16_S1 external_label
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e1 fffe beqzc at,0+0064 <text_label\+0x64>
64: R_MICROMIPS_PC16_S1 external_label
\.\.\.

12
gas/testsuite/gas/mips/micromips@branch-misc-4-64.d
View File

@ -9,27 +9,23 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <foo\+0x[0-9a-f]+>
[0-9a-f]+ <[^>]*> 40e0 0000 bc [0-9a-f]+ <\.Lfoo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar\-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <\.Lfoo\+0x[0-9a-f]+>
[0-9a-f]+ <[^>]*> 40e0 0000 bc [0-9a-f]+ <\.Lfoo\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.Lbar-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.
Disassembly of section \.init:
[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <bar\+0x[0-9a-f]+>
[0-9a-f]+ <[^>]*> 40e0 0000 bc [0-9a-f]+ <\.Lbar>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo\-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 0000 b [0-9a-f]+ <\.Lbar\+0x[0-9a-f]+>
[0-9a-f]+ <[^>]*> 40e0 0000 bc [0-9a-f]+ <\.Lbar\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.Lfoo-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

12
gas/testsuite/gas/mips/micromips@branch-misc-4.d
View File

@ -9,19 +9,15 @@
Disassembly of section \.text:
\.\.\.
([0-9a-f]+) <[^>]*> 9400 fffe b \1 <foo>
([0-9a-f]+) <[^>]*> 40e0 fffe bc \1 <foo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 bar
[0-9a-f]+ <[^>]*> 0c00 nop
([0-9a-f]+) <[^>]*> 9400 fffe b \1 <\.Lfoo>
([0-9a-f]+) <[^>]*> 40e0 fffe bc \1 <\.Lfoo>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.Lbar
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.
Disassembly of section \.init:
([0-9a-f]+) <[^>]*> 9400 fffe b \1 <bar>
([0-9a-f]+) <[^>]*> 40e0 fffe bc \1 <bar>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo
[0-9a-f]+ <[^>]*> 0c00 nop
([0-9a-f]+) <[^>]*> 9400 fffe b \1 <\.Lbar>
([0-9a-f]+) <[^>]*> 40e0 fffe bc \1 <\.Lbar>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.Lfoo
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

22
gas/testsuite/gas/mips/micromips@branch-misc-5-64.d
View File

@ -9,20 +9,16 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 0000 b 0+0004 <g6\+0x4>
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0+0004 <g6\+0x4>
0: R_MICROMIPS_PC16_S1 x1\-0x4
0: R_MIPS_NONE \*ABS\*\-0x4
0: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 0000 b 0+000a <g6\+0xa>
6: R_MICROMIPS_PC16_S1 x2\-0x4
6: R_MIPS_NONE \*ABS\*\-0x4
6: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 0000 b 0+0010 <g6\+0x10>
c: R_MICROMIPS_PC16_S1 \.Ldata\-0x4
c: R_MIPS_NONE \*ABS\*\-0x4
c: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0+0008 <g6\+0x8>
4: R_MICROMIPS_PC16_S1 x2\-0x4
4: R_MIPS_NONE \*ABS\*\-0x4
4: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0+000c <g6\+0xc>
8: R_MICROMIPS_PC16_S1 \.Ldata\-0x4
8: R_MIPS_NONE \*ABS\*\-0x4
8: R_MIPS_NONE \*ABS\*\-0x4
\.\.\.

14
gas/testsuite/gas/mips/micromips@branch-misc-5.d
View File

@ -9,14 +9,10 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 fffe b 0+0000 <g6>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 0+0000 <g6>
0: R_MICROMIPS_PC16_S1 x1
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 fffe b 0+0006 <g6\+0x6>
6: R_MICROMIPS_PC16_S1 x2
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 fffe b 0+000c <g6\+0xc>
c: R_MICROMIPS_PC16_S1 \.Ldata
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e0 fffe bc 0+0004 <g6\+0x4>
4: R_MICROMIPS_PC16_S1 x2
[0-9a-f]+ <[^>]*> 40e0 fffe bc 0+0008 <g6\+0x8>
8: R_MICROMIPS_PC16_S1 \.Ldata
\.\.\.

22
gas/testsuite/gas/mips/micromips@branch-misc-5pic-64.d
View File

@ -9,20 +9,16 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 0000 b 0+0004 <g6\+0x4>
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0+0004 <g6\+0x4>
0: R_MICROMIPS_PC16_S1 x1\-0x4
0: R_MIPS_NONE \*ABS\*\-0x4
0: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 0000 b 0+000a <g6\+0xa>
6: R_MICROMIPS_PC16_S1 x2\-0x4
6: R_MIPS_NONE \*ABS\*\-0x4
6: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 0000 b 0+0010 <g6\+0x10>
c: R_MICROMIPS_PC16_S1 \.Ldata\-0x4
c: R_MIPS_NONE \*ABS\*\-0x4
c: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0+0008 <g6\+0x8>
4: R_MICROMIPS_PC16_S1 x2\-0x4
4: R_MIPS_NONE \*ABS\*\-0x4
4: R_MIPS_NONE \*ABS\*\-0x4
[0-9a-f]+ <[^>]*> 40e0 0000 bc 0+000c <g6\+0xc>
8: R_MICROMIPS_PC16_S1 \.Ldata\-0x4
8: R_MIPS_NONE \*ABS\*\-0x4
8: R_MIPS_NONE \*ABS\*\-0x4
\.\.\.

14
gas/testsuite/gas/mips/micromips@branch-misc-5pic.d
View File

@ -9,14 +9,10 @@
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 9400 fffe b 0+0000 <g6>
[0-9a-f]+ <[^>]*> 40e0 fffe bc 0+0000 <g6>
0: R_MICROMIPS_PC16_S1 x1
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 fffe b 0+0006 <g6\+0x6>
6: R_MICROMIPS_PC16_S1 x2
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 9400 fffe b 0+000c <g6\+0xc>
c: R_MICROMIPS_PC16_S1 \.Ldata
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e0 fffe bc 0+0004 <g6\+0x4>
4: R_MICROMIPS_PC16_S1 x2
[0-9a-f]+ <[^>]*> 40e0 fffe bc 0+0008 <g6\+0x8>
8: R_MICROMIPS_PC16_S1 \.Ldata
\.\.\.

3
gas/testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d
View File

@ -28,6 +28,5 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 4c09 addiu sp,sp,16
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45bf jrc ra
\.\.\.

3
gas/testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d
View File

@ -32,6 +32,5 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 4c09 addiu sp,sp,16
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45bf jrc ra
\.\.\.

3
gas/testsuite/gas/mips/micromips@jal-svr4pic-local.d
View File

@ -27,6 +27,5 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 4c11 addiu sp,sp,32
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45bf jrc ra
\.\.\.

6
gas/testsuite/gas/mips/micromips@loc-swap-dis.d
View File

@ -9,15 +9,13 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c90 move a0,s0
[0-9a-f]+ <[^>]*> 4584 jr a0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a4 jrc a0
[0-9a-f]+ <[^>]*> 4584 jr a0
[0-9a-f]+ <[^>]*> 0ff0 move ra,s0
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c90 move a0,s0
[0-9a-f]+ <[^>]*> 0ff0 move ra,s0
[0-9a-f]+ <[^>]*> 459f jr ra
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45bf jrc ra
[0-9a-f]+ <[^>]*> 0c90 move a0,s0
[0-9a-f]+ <[^>]*> 45c4 jalr a0
[0-9a-f]+ <[^>]*> 0000 0000 nop

30
gas/testsuite/gas/mips/micromips@loc-swap.d
View File

@ -44,19 +44,19 @@ Raw dump of debug contents of section \.debug_line:
\[0x.*\] Extended opcode 2: set Address to 0x1
\[0x.*\] Special opcode 11: advance Address by 0 to 0x1 and Line by 6 to 7
\[0x.*\] Special opcode 35: advance Address by 2 to 0x3 and Line by 2 to 9
\[0x.*\] Special opcode 64: advance Address by 4 to 0x7 and Line by 3 to 12
\[0x.*\] Special opcode 7: advance Address by 0 to 0x7 and Line by 2 to 14
\[0x.*\] Special opcode 64: advance Address by 4 to 0xb and Line by 3 to 17
\[0x.*\] Special opcode 7: advance Address by 0 to 0xb and Line by 2 to 19
\[0x.*\] Special opcode 64: advance Address by 4 to 0xf and Line by 3 to 22
\[0x.*\] Special opcode 35: advance Address by 2 to 0x11 and Line by 2 to 24
\[0x.*\] Special opcode 64: advance Address by 4 to 0x15 and Line by 3 to 27
\[0x.*\] Special opcode 35: advance Address by 2 to 0x17 and Line by 2 to 29
\[0x.*\] Special opcode 92: advance Address by 6 to 0x1d and Line by 3 to 32
\[0x.*\] Special opcode 35: advance Address by 2 to 0x1f and Line by 2 to 34
\[0x.*\] Special opcode 92: advance Address by 6 to 0x25 and Line by 3 to 37
\[0x.*\] Special opcode 35: advance Address by 2 to 0x27 and Line by 2 to 39
\[0x.*\] Special opcode 120: advance Address by 8 to 0x2f and Line by 3 to 42
\[0x.*\] Special opcode 35: advance Address by 2 to 0x31 and Line by 2 to 44
\[0x.*\] Advance PC by 23 to 0x48
\[0x.*\] Special opcode 36: advance Address by 2 to 0x5 and Line by 3 to 12
\[0x.*\] Special opcode 7: advance Address by 0 to 0x5 and Line by 2 to 14
\[0x.*\] Special opcode 64: advance Address by 4 to 0x9 and Line by 3 to 17
\[0x.*\] Special opcode 7: advance Address by 0 to 0x9 and Line by 2 to 19
\[0x.*\] Special opcode 64: advance Address by 4 to 0xd and Line by 3 to 22
\[0x.*\] Special opcode 35: advance Address by 2 to 0xf and Line by 2 to 24
\[0x.*\] Special opcode 36: advance Address by 2 to 0x11 and Line by 3 to 27
\[0x.*\] Special opcode 35: advance Address by 2 to 0x13 and Line by 2 to 29
\[0x.*\] Special opcode 92: advance Address by 6 to 0x19 and Line by 3 to 32
\[0x.*\] Special opcode 35: advance Address by 2 to 0x1b and Line by 2 to 34
\[0x.*\] Special opcode 92: advance Address by 6 to 0x21 and Line by 3 to 37
\[0x.*\] Special opcode 35: advance Address by 2 to 0x23 and Line by 2 to 39
\[0x.*\] Special opcode 120: advance Address by 8 to 0x2b and Line by 3 to 42
\[0x.*\] Special opcode 35: advance Address by 2 to 0x2d and Line by 2 to 44
\[0x.*\] Advance PC by 23 to 0x44
\[0x.*\] Extended opcode 1: End of Sequence

98
gas/testsuite/gas/mips/micromips@relax-at.d
View File

@ -11,13 +11,12 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45da jalr k0
[0-9a-f]+ <[^>]*> 0000 0000 nop
@ -26,79 +25,71 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45da jalr k0
[0-9a-f]+ <[^>]*> 0000 0000 nop
@ -107,7 +98,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45da jalr k0
[0-9a-f]+ <[^>]*> 0000 0000 nop
@ -116,7 +107,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -125,7 +116,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -134,7 +125,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -143,7 +134,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -152,7 +143,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -161,7 +152,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -170,7 +161,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -179,7 +170,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -188,7 +179,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45fa jalrs k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -197,7 +188,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> ff5c 0002 lw k0,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0187 addiu k0,k0,391
[0-9a-f]+ <[^>]*> 335a 0175 addiu k0,k0,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45fa jalrs k0
[0-9a-f]+ <[^>]*> 0c00 nop
@ -206,8 +197,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
[0-9a-f]+ <[^>]*> ff5c 0000 lw k0,0\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
@ -221,8 +211,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -230,8 +219,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -239,8 +227,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -248,8 +235,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -257,8 +243,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -266,8 +251,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -275,8 +259,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -284,8 +267,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 335a 0001 addiu k0,k0,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 459a jr k0
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45ba jrc k0
([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop

7
gas/testsuite/gas/mips/micromips@relax-swap3.d
View File

@ -10,13 +10,12 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_HI16 bar
[0-9a-f]+ <[^>]*> 3042 0000 addiu v0,v0,0
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
[0-9a-f]+ <[^>]*> 4583 jr v1
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a3 jrc v1
[0-9a-f]+ <[^>]*> 41a2 0000 lui v0,0x0
[ ]*[0-9a-f]+: R_MICROMIPS_HI16 bar
[0-9a-f]+ <[^>]*> 3042 0000 addiu v0,v0,0
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
[0-9a-f]+ <[^>]*> 8dff beqz v1,[0-9a-f]+ <[^>]*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
[0-9a-f]+ <[^>]*> 40e3 fffe beqzc v1,[0-9a-f]+ <[^>]*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

98
gas/testsuite/gas/mips/micromips@relax.d
View File

@ -11,13 +11,12 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45c1 jalr at
[0-9a-f]+ <[^>]*> 0000 0000 nop
@ -26,79 +25,71 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45c1 jalr at
[0-9a-f]+ <[^>]*> 0000 0000 nop
@ -107,7 +98,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45c1 jalr at
[0-9a-f]+ <[^>]*> 0000 0000 nop
@ -116,7 +107,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -125,7 +116,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -134,7 +125,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -143,7 +134,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -152,7 +143,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -161,7 +152,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -170,7 +161,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -179,7 +170,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -188,7 +179,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45e1 jalrs at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -197,7 +188,7 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> fc3c 0002 lw at,2\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0187 addiu at,at,391
[0-9a-f]+ <[^>]*> 3021 0175 addiu at,at,373
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 45e1 jalrs at
[0-9a-f]+ <[^>]*> 0c00 nop
@ -206,8 +197,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
[0-9a-f]+ <[^>]*> fc3c 0000 lw at,0\(gp\)
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
@ -221,8 +211,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 94a4 fffe beq a0,a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -230,8 +219,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 40c2 fffe bgtz v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -239,8 +227,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4083 fffe blez v1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -248,8 +235,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4044 fffe bgez a0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -257,8 +243,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4005 fffe bltz a1,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -266,8 +251,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -275,8 +259,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4380 fffe bc1f \1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop
@ -284,8 +267,7 @@ Disassembly of section \.text:
[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 \.text
[0-9a-f]+ <[^>]*> 3021 0001 addiu at,at,1
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.text
[0-9a-f]+ <[^>]*> 4581 jr at
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 45a1 jrc at
([0-9a-f]+) <[^>]*> 4042 fffe bgez v0,\1 <.*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
[0-9a-f]+ <[^>]*> 0c00 nop

1
gas/testsuite/gas/mips/mips.exp
View File

@ -1345,6 +1345,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "micromips"
run_dump_test "micromips-trap"
run_dump_test "micromips-compact"
run_dump_test "micromips-insn32"
run_dump_test "micromips-noinsn32"
run_list_test "micromips" "-mips32r2 -32 -mfp64 -minsn32" \

7
ld/ChangeLog
View File

@ -1,3 +1,10 @@
2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
patterns for branch compaction.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
Likewise.
2016-07-27 Nick Clifton <nickc@redhat.com>
* testsuite/ld-gc/personality.d: Use "target cfi" to restrict the

13
ld/testsuite/ld-mips-elf/micromips-branch-absolute-addend.d
View File

@ -8,15 +8,12 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 2c54 b 0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 2c51 bal 0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 40e0 2c54 bc 0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 4060 2c52 bal 0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 2c4d bltzal zero,0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 4020 2c4e bltzal zero,0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 2c49 beqz v0,0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 2c46 bnez v0,0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e2 2c4a beqzc v0,0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 40a2 2c48 bnezc v0,0*123468ac <bar\+0x1233>
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

13
ld/testsuite/ld-mips-elf/micromips-branch-absolute.d
View File

@ -8,15 +8,12 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 9400 0118 b 0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 4060 0115 bal 0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 40e0 0118 bc 0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 4060 0116 bal 0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 4020 0111 bltzal zero,0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 4020 0112 bltzal zero,0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 9402 010d beqz v0,0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> b402 010a bnez v0,0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 0c00 nop
[0-9a-f]+ <[^>]*> 40e2 010e beqzc v0,0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 40a2 010c bnezc v0,0+001234 <foo\+0x234>
[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
"j".
2016-07-27 Graham Markall <graham.markall@embecosm.com>
* arc-nps400-tbl.h: Change block comments to GNU format.

22
opcodes/micromips-opc.c
View File

@ -305,9 +305,11 @@ const struct mips_opcode micromips_opcodes[] =
{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* beq 0, 0 */
{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* bgez 0 */
/* BC is next to B so that we easily find it when converting a normal
branch to a compact one. */
{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */
{"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, 0 }, /* bgezal 0 */
{"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, 0 }, /* bgezals 0 */
{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
@ -366,12 +368,14 @@ const struct mips_opcode micromips_opcodes[] =
{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 },
{"beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 },
{"beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 },
{"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* beqz */
{"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* beqz */
{"beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
/* BEQZC is next to BEQ so that we easily find it when converting a normal
branch to a compact one. */
{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 },
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, 0 },
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
@ -422,12 +426,14 @@ const struct mips_opcode micromips_opcodes[] =
{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, 0 },
{"bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 },
{"bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 },
{"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* bnez */
{"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* bnez */
{"bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
/* BNEZC is next to BNE so that we easily find it when converting a normal
branch to a compact one. */
{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, 0 },
{"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
@ -697,10 +703,6 @@ const struct mips_opcode micromips_opcodes[] =
/* This macro is after the real instruction so that it only matches with
-minsn32. */
{"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1, 0, 0 },
{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 },
/* This macro is after the real instruction so that it only matches with
-minsn32. */
{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 },
{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb */
{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs.hb */
{"j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, /* jr */
@ -712,6 +714,12 @@ const struct mips_opcode micromips_opcodes[] =
assembler, but will never match user input (because the line above
will match first). */
{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 },
/* JRC is close to JR and J so that we easily find it when converting
a normal jump to a compact one. */
{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 },
/* This macro is after the real instruction so that it only matches with
-minsn32. */
{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 },
{"jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, 0 },
{"jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, 0 },
{"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 },

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