2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>

* s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> * gas/s390/zarch-z990.d (idte): Fix operand format.
18 years ago · 725a9891bc
5 changed files with 11 additions and 3 deletions
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@ -1,3 +1,7 @@
+2008-05-27  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* gas/s390/zarch-z990.d (idte): Fix operand format.
+
 2008-05-22  H.J. Lu  <hongjiu.lu@intel.com>

 	* gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and
--- a/gas/testsuite/gas/s390/zarch-z990.d
+++ b/gas/testsuite/gas/s390/zarch-z990.d
@ -45,7 +45,7 @@ Disassembly of section .text:
 .*:	eb 6f 50 00 80 80 [	 ]*icmh	%r6,15,-524288\(%r5\)
 .*:	eb 6f 50 00 80 81 [	 ]*icmy	%r6,15,-524288\(%r5\)
 .*:	e3 65 a0 00 80 73 [	 ]*icy	%r6,-524288\(%r5,%r10\)
-.*:	b9 8e 50 69 [	 ]*idte	%r6,%r9,%r5
+.*:	b9 8e 50 69 [	 ]*idte	%r6,%r5,%r9
 .*:	eb 69 50 00 80 9a [	 ]*lamy	%a6,%a9,-524288\(%r5\)
 .*:	e3 65 a0 00 80 71 [	 ]*lay	%r6,-524288\(%r5,%r10\)
 .*:	e3 65 a0 00 80 76 [	 ]*lb	%r6,-524288\(%r5,%r10\)
--- a/gas/testsuite/gas/s390/zarch-z990.s
+++ b/gas/testsuite/gas/s390/zarch-z990.s
@ -39,7 +39,7 @@ foo:
 	icmh	%r6,15,-524288(%r5)
 	icmy	%r6,15,-524288(%r5)
 	icy	%r6,-524288(%r5,%r10)
-	idte	%r6,%r9,%r5
+	idte	%r6,%r5,%r9
 	lamy	%a6,%a9,-524288(%r5)
 	lay	%r6,-524288(%r5,%r10)
 	lb	%r6,-524288(%r5,%r10)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@ -1,3 +1,7 @@
+2008-05-27  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
+
 2008-05-22  H.J. Lu  <hongjiu.lu@intel.com>

 	* i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@ -268,7 +268,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
-#define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 }           /* e.g. idte  */
+#define INSTR_RRF_R0RR   4, { R_24,R_16,R_28,0,0,0 }           /* e.g. idte  */
 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. fixr  */
 #define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 }          /* e.g. cfebr */
 #define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */