x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit mode

Update x86 disassembler to handle the unsupported static rounding in
vcvt[u]si2sd in 32-bit mode.

gas/

	PR binutils/23655
	* testsuite/gas/i386/evex.d: Updated.

opcodes/

	PR binutils/23655
	* i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
	vcvtsi2sd%LQ and vcvtusi2sd%LQ.
	* i386-dis.c (EXxEVexR64): New.
	(evex_rounding_64_mode): Likewise.
	(OP_Rounding): Handle evex_rounding_64_mode.

gas/ChangeLog

@@ -1,3 +1,8 @@
+2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/23655
+	* testsuite/gas/i386/evex.d: Updated.
+
 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/23655

gas/testsuite/gas/i386/evex.d

@@ -8,9 +8,9 @@ Disassembly of section .text:
 
 0+ <_start>:
  +[a-f0-9]+:	62 f1 d6 38 2a f0    	vcvtsi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
- +[a-f0-9]+:	62 f1 d7 38 2a f0    	vcvtsi2sdl %eax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+:	62 f1 d7 38 2a f0    	vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
  +[a-f0-9]+:	62 f1 d6 08 7b f0    	vcvtusi2ssl %eax,%xmm5,%xmm6
  +[a-f0-9]+:	62 f1 d7 08 7b f0    	vcvtusi2sdl %eax,%xmm5,%xmm6
  +[a-f0-9]+:	62 f1 d6 38 7b f0    	vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
- +[a-f0-9]+:	62 f1 d7 38 7b f0    	vcvtusi2sdl %eax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+:	62 f1 d7 38 7b f0    	vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
 #pass

opcodes/ChangeLog

@@ -1,3 +1,12 @@
+2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/23655
+	* i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
+	vcvtsi2sd%LQ and vcvtusi2sd%LQ.
+	* i386-dis.c (EXxEVexR64): New.
+	(evex_rounding_64_mode): Likewise.
+	(OP_Rounding): Handle evex_rounding_64_mode.
+
 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/23655

opcodes/i386-dis-evex.h

@@ -3051,7 +3051,7 @@ static const struct dis386 evex_table[][256] = {
   /* EVEX_W_0F2A_P_3 */
   {
     { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, Ed }, 0 },
-    { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
+    { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, EXxEVexR64, Edqa }, 0 },
   },
   /* EVEX_W_0F2B_P_0 */
   {
@@ -3393,7 +3393,7 @@ static const struct dis386 evex_table[][256] = {
   /* EVEX_W_0F7B_P_3 */
   {
     { "vcvtusi2sd%LQ",	{ XMScalar, VexScalar, Ed }, 0 },
-    { "vcvtusi2sd%LQ",	{ XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
+    { "vcvtusi2sd%LQ",	{ XMScalar, VexScalar, EXxEVexR64, Edqa }, 0 },
   },
   /* EVEX_W_0F7E_P_1 */
   {

opcodes/i386-dis.c

@@ -448,6 +448,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define VPCOM { VPCOM_Fixup, 0 }
 
 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
+#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 
 #define XMask { OP_Mask, mask_mode }
@@ -633,6 +634,8 @@ enum
 
   /* Static rounding.  */
   evex_rounding_mode,
+  /* Static rounding, 64-bit mode only.  */
+  evex_rounding_64_mode,
   /* Supress all exceptions.  */
   evex_sae_mode,
 
@@ -17950,11 +17953,19 @@ OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 {
   if (!vex.evex
       || (bytemode != evex_rounding_mode
+	  && bytemode != evex_rounding_64_mode
 	  && bytemode != evex_sae_mode))
     abort ();
   if (modrm.mod == 3 && vex.b)
     switch (bytemode)
       {
+      case evex_rounding_64_mode:
+	if (address_mode != mode_64bit)
+	  {
+	    oappend ("(bad)");
+	    break;
+	  }
+	/* Fall through.  */
       case evex_rounding_mode:
 	oappend (names_rounding[vex.ll]);
 	break;