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aarch64: Add the SME2 shift instructions 

There are two instruction formats here:

- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
  or four registers.

- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
  four registers.

These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.
users/aburgess/try-core-file-pid0
Richard Sandiford 3 years ago
parent
ce623e7aa4
commit
6efa660124
25 changed files with 1066 additions and 508 deletions
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  1. 17
      gas/config/tc-aarch64.c
  2. 3
      gas/testsuite/gas/aarch64/sme2-27-invalid.d
  3. 31
      gas/testsuite/gas/aarch64/sme2-27-invalid.l
  4. 25
      gas/testsuite/gas/aarch64/sme2-27-invalid.s
  5. 3
      gas/testsuite/gas/aarch64/sme2-27-noarch.d
  6. 50
      gas/testsuite/gas/aarch64/sme2-27-noarch.l
  7. 62
      gas/testsuite/gas/aarch64/sme2-27.d
  8. 71
      gas/testsuite/gas/aarch64/sme2-27.s
  9. 3
      gas/testsuite/gas/aarch64/sme2-28-invalid.d
  10. 19
      gas/testsuite/gas/aarch64/sme2-28-invalid.l
  11. 11
      gas/testsuite/gas/aarch64/sme2-28-invalid.s
  12. 3
      gas/testsuite/gas/aarch64/sme2-28-noarch.d
  13. 26
      gas/testsuite/gas/aarch64/sme2-28-noarch.l
  14. 34
      gas/testsuite/gas/aarch64/sme2-28.d
  15. 29
      gas/testsuite/gas/aarch64/sme2-28.s
  16. 3
      include/opcode/aarch64.h
  17. 23
      opcodes/aarch64-asm-2.c
  18. 14
      opcodes/aarch64-asm.c
  19. 1
      opcodes/aarch64-asm.h
  20. 1092
      opcodes/aarch64-dis-2.c
  21. 17
      opcodes/aarch64-dis.c
  22. 1
      opcodes/aarch64-dis.h
  23. 2
      opcodes/aarch64-opc-2.c
  24. 12
      opcodes/aarch64-opc.c
  25. 22
      opcodes/aarch64-tbl.h

17
gas/config/tc-aarch64.c
View File

@ -349,6 +349,13 @@ struct reloc_entry
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
| REG_TYPE(Z) | REG_TYPE(P)) \
/* Likewise, but with predicate-as-counter registers added. */ \
MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP_PN, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
| REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
| REG_TYPE(Z) | REG_TYPE(P) | REG_TYPE(PN)) \
/* Any integer register; used for error messages only. */ \
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
@ -6527,9 +6534,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
clear_error ();
skip_whitespace (str);
if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
AARCH64_FEATURE_SVE
| AARCH64_FEATURE_SVE2))
if (AARCH64_CPU_HAS_FEATURE (*opcode->avariant, AARCH64_FEATURE_SME2))
imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP_PN;
else if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
AARCH64_FEATURE_SVE
| AARCH64_FEATURE_SVE2))
imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP;
else
imm_reg_type = REG_TYPE_R_ZR_BHSDQ_V;
@ -6892,6 +6901,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
case AARCH64_OPND_SME_SHRIMM4:
case AARCH64_OPND_SME_SHRIMM5:
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:

3
gas/testsuite/gas/aarch64/sme2-27-invalid.d
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: sme2-27-invalid.s
#error_output: sme2-27-invalid.l

31
gas/testsuite/gas/aarch64/sme2-27-invalid.l
View File

@ -0,0 +1,31 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshr 0,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqrshr z0\.h,0,#1'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.h,{z1\.s-z2\.s},#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},#17'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.s,{z0\.d-z1\.d},#1'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z1\.d}, #1
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z1\.s}, #1
[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},x0'
[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},z0\.s'
[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},p0'
[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},pn0'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z1\.s-z4\.s},#1'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z2\.s-z5\.s},#1'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z3\.s-z6\.s},#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#-1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#33'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.b,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z3\.s}, #1
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z3\.d}, #1
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.b,{z0\.d-z3\.d},#65'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z3\.s}, #65
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z3\.d}, #65

25
gas/testsuite/gas/aarch64/sme2-27-invalid.s
View File

@ -0,0 +1,25 @@
.equ x0, 1
.equ z0.s, 2
.equ p0, 3
.equ pn0, 4
sqrshr 0, { z0.s - z1.s }, #1
sqrshr z0.h, 0, #1
sqrshr z0.h, { z1.s - z2.s }, #1
sqrshr z0.h, { z0.s - z1.s }, #0
sqrshr z0.h, { z0.s - z1.s }, #17
sqrshr z0.s, { z0.d - z1.d }, #1
sqrshr z0.h, { z0.s - z1.s }, x0
sqrshr z0.h, { z0.s - z1.s }, z0.s
sqrshr z0.h, { z0.s - z1.s }, p0
sqrshr z0.h, { z0.s - z1.s }, pn0
sqrshr z0.b, { z1.s - z4.s }, #1
sqrshr z0.b, { z2.s - z5.s }, #1
sqrshr z0.b, { z3.s - z6.s }, #1
sqrshr z0.b, { z0.s - z3.s }, #-1
sqrshr z0.b, { z0.s - z3.s }, #0
sqrshr z0.b, { z0.s - z3.s }, #33
sqrshr z0.b, { z0.d - z3.d }, #1
sqrshr z0.b, { z0.d - z3.d }, #65 // Double error

3
gas/testsuite/gas/aarch64/sme2-27-noarch.d
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sme2-27.s
#error_output: sme2-27-noarch.l

50
gas/testsuite/gas/aarch64/sme2-27-noarch.l
View File

@ -0,0 +1,50 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.h,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z30\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#16'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z14\.h,{z22\.s-z23\.s},#7'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#x0'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#p0'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#pn0'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z28\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z0\.s-z3\.s},#32'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z6\.b,{z12\.s-z15\.s},#25'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z28\.d-z31\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.d-z3\.d},#64'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z25\.h,{z20\.d-z23\.d},#50'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.h,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z30\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.s-z1\.s},#16'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z14\.h,{z22\.s-z23\.s},#7'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z28\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z0\.s-z3\.s},#32'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z6\.b,{z12\.s-z15\.s},#25'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z28\.d-z31\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.d-z3\.d},#64'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z25\.h,{z20\.d-z23\.d},#50'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.h,{z0\.s-z1\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z30\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.s-z1\.s},#16'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z14\.h,{z22\.s-z23\.s},#7'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z28\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z0\.s-z3\.s},#32'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z6\.b,{z12\.s-z15\.s},#25'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z28\.d-z31\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.d-z3\.d},#64'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z25\.h,{z20\.d-z23\.d},#50'

62
gas/testsuite/gas/aarch64/sme2-27.d
View File

@ -0,0 +1,62 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: c1efd400 sqrshr z0\.h, {z0\.s-z1\.s}, #1
[^:]+: c1efd41f sqrshr z31\.h, {z0\.s-z1\.s}, #1
[^:]+: c1efd7c0 sqrshr z0\.h, {z30\.s-z31\.s}, #1
[^:]+: c1e0d400 sqrshr z0\.h, {z0\.s-z1\.s}, #16
[^:]+: c1e9d6ce sqrshr z14\.h, {z22\.s-z23\.s}, #7
[^:]+: c1efd400 sqrshr z0\.h, {z0\.s-z1\.s}, #1
[^:]+: c1eed400 sqrshr z0\.h, {z0\.s-z1\.s}, #2
[^:]+: c1edd400 sqrshr z0\.h, {z0\.s-z1\.s}, #3
[^:]+: c1ecd400 sqrshr z0\.h, {z0\.s-z1\.s}, #4
[^:]+: c17fd800 sqrshr z0\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fd81f sqrshr z31\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdb80 sqrshr z0\.b, {z28\.s-z31\.s}, #1
[^:]+: c160d800 sqrshr z0\.b, {z0\.s-z3\.s}, #32
[^:]+: c167d986 sqrshr z6\.b, {z12\.s-z15\.s}, #25
[^:]+: c1ffd800 sqrshr z0\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffd81f sqrshr z31\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdb80 sqrshr z0\.h, {z28\.d-z31\.d}, #1
[^:]+: c1a0d800 sqrshr z0\.h, {z0\.d-z3\.d}, #64
[^:]+: c1aeda99 sqrshr z25\.h, {z20\.d-z23\.d}, #50
[^:]+: c13fd800 \.inst 0xc13fd800 ; undefined
[^:]+: c120d800 \.inst 0xc120d800 ; undefined
[^:]+: c1ffd400 sqrshru z0\.h, {z0\.s-z1\.s}, #1
[^:]+: c1ffd41f sqrshru z31\.h, {z0\.s-z1\.s}, #1
[^:]+: c1ffd7c0 sqrshru z0\.h, {z30\.s-z31\.s}, #1
[^:]+: c1f0d400 sqrshru z0\.h, {z0\.s-z1\.s}, #16
[^:]+: c1f9d6ce sqrshru z14\.h, {z22\.s-z23\.s}, #7
[^:]+: c17fd840 sqrshru z0\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fd85f sqrshru z31\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdbc0 sqrshru z0\.b, {z28\.s-z31\.s}, #1
[^:]+: c160d840 sqrshru z0\.b, {z0\.s-z3\.s}, #32
[^:]+: c167d9c6 sqrshru z6\.b, {z12\.s-z15\.s}, #25
[^:]+: c1ffd840 sqrshru z0\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffd85f sqrshru z31\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdbc0 sqrshru z0\.h, {z28\.d-z31\.d}, #1
[^:]+: c1a0d840 sqrshru z0\.h, {z0\.d-z3\.d}, #64
[^:]+: c1aedad9 sqrshru z25\.h, {z20\.d-z23\.d}, #50
[^:]+: c1efd420 uqrshr z0\.h, {z0\.s-z1\.s}, #1
[^:]+: c1efd43f uqrshr z31\.h, {z0\.s-z1\.s}, #1
[^:]+: c1efd7e0 uqrshr z0\.h, {z30\.s-z31\.s}, #1
[^:]+: c1e0d420 uqrshr z0\.h, {z0\.s-z1\.s}, #16
[^:]+: c1e9d6ee uqrshr z14\.h, {z22\.s-z23\.s}, #7
[^:]+: c17fd820 uqrshr z0\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fd83f uqrshr z31\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdba0 uqrshr z0\.b, {z28\.s-z31\.s}, #1
[^:]+: c160d820 uqrshr z0\.b, {z0\.s-z3\.s}, #32
[^:]+: c167d9a6 uqrshr z6\.b, {z12\.s-z15\.s}, #25
[^:]+: c1ffd820 uqrshr z0\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffd83f uqrshr z31\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdba0 uqrshr z0\.h, {z28\.d-z31\.d}, #1
[^:]+: c1a0d820 uqrshr z0\.h, {z0\.d-z3\.d}, #64
[^:]+: c1aedab9 uqrshr z25\.h, {z20\.d-z23\.d}, #50
[^:]+: c13fd820 \.inst 0xc13fd820 ; undefined
[^:]+: c120d820 \.inst 0xc120d820 ; undefined

71
gas/testsuite/gas/aarch64/sme2-27.s
View File

@ -0,0 +1,71 @@
.equ x0, 1
.equ z0.s, 2
.equ p0, 3
.equ pn0, 4
sqrshr z0.h, { z0.s - z1.s }, #1
sqrshr z31.h, { z0.s - z1.s }, #1
sqrshr z0.h, { z30.s - z31.s }, #1
sqrshr z0.h, { z0.s - z1.s }, #16
sqrshr z14.h, { z22.s - z23.s }, #7
sqrshr z0.h, { z0.s - z1.s }, #x0
sqrshr z0.h, { z0.s - z1.s }, #z0.s
sqrshr z0.h, { z0.s - z1.s }, #p0
sqrshr z0.h, { z0.s - z1.s }, #pn0
sqrshr z0.b, { z0.s - z3.s }, #1
sqrshr z31.b, { z0.s - z3.s }, #1
sqrshr z0.b, { z28.s - z31.s }, #1
sqrshr z0.b, { z0.s - z3.s }, #32
sqrshr z6.b, { z12.s - z15.s }, #25
sqrshr z0.h, { z0.d - z3.d }, #1
sqrshr z31.h, { z0.d - z3.d }, #1
sqrshr z0.h, { z28.d - z31.d }, #1
sqrshr z0.h, { z0.d - z3.d }, #64
sqrshr z25.h, { z20.d - z23.d }, #50
// Invalid SQRSHR
.inst 0xc13fd800
.inst 0xc120d800
sqrshru z0.h, { z0.s - z1.s }, #1
sqrshru z31.h, { z0.s - z1.s }, #1
sqrshru z0.h, { z30.s - z31.s }, #1
sqrshru z0.h, { z0.s - z1.s }, #16
sqrshru z14.h, { z22.s - z23.s }, #7
sqrshru z0.b, { z0.s - z3.s }, #1
sqrshru z31.b, { z0.s - z3.s }, #1
sqrshru z0.b, { z28.s - z31.s }, #1
sqrshru z0.b, { z0.s - z3.s }, #32
sqrshru z6.b, { z12.s - z15.s }, #25
sqrshru z0.h, { z0.d - z3.d }, #1
sqrshru z31.h, { z0.d - z3.d }, #1
sqrshru z0.h, { z28.d - z31.d }, #1
sqrshru z0.h, { z0.d - z3.d }, #64
sqrshru z25.h, { z20.d - z23.d }, #50
uqrshr z0.h, { z0.s - z1.s }, #1
uqrshr z31.h, { z0.s - z1.s }, #1
uqrshr z0.h, { z30.s - z31.s }, #1
uqrshr z0.h, { z0.s - z1.s }, #16
uqrshr z14.h, { z22.s - z23.s }, #7
uqrshr z0.b, { z0.s - z3.s }, #1
uqrshr z31.b, { z0.s - z3.s }, #1
uqrshr z0.b, { z28.s - z31.s }, #1
uqrshr z0.b, { z0.s - z3.s }, #32
uqrshr z6.b, { z12.s - z15.s }, #25
uqrshr z0.h, { z0.d - z3.d }, #1
uqrshr z31.h, { z0.d - z3.d }, #1
uqrshr z0.h, { z28.d - z31.d }, #1
uqrshr z0.h, { z0.d - z3.d }, #64
uqrshr z25.h, { z20.d - z23.d }, #50
// Invalid UQRSHR
.inst 0xc13fd820
.inst 0xc120d820

3
gas/testsuite/gas/aarch64/sme2-28-invalid.d
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: sme2-28-invalid.s
#error_output: sme2-28-invalid.l

19
gas/testsuite/gas/aarch64/sme2-28-invalid.l
View File

@ -0,0 +1,19 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrshrn 0,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqrshrn z0\.b,0,#1'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z1\.s-z4\.s},#1'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z2\.s-z5\.s},#1'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z3\.s-z6\.s},#1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#-1'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#33'
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z3\.s}, #1
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z3\.d}, #1
[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{z0\.d-z3\.d},#65'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z3\.s}, #65
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z3\.d}, #65

11
gas/testsuite/gas/aarch64/sme2-28-invalid.s
View File

@ -0,0 +1,11 @@
sqrshrn 0, { z0.s - z3.s }, #1
sqrshrn z0.b, 0, #1
sqrshrn z0.b, { z1.s - z4.s }, #1
sqrshrn z0.b, { z2.s - z5.s }, #1
sqrshrn z0.b, { z3.s - z6.s }, #1
sqrshrn z0.b, { z0.s - z3.s }, #-1
sqrshrn z0.b, { z0.s - z3.s }, #0
sqrshrn z0.b, { z0.s - z3.s }, #33
sqrshrn z0.b, { z0.d - z3.d }, #1
sqrshrn z0.b, { z0.d - z3.d }, #65 // Double error

3
gas/testsuite/gas/aarch64/sme2-28-noarch.d
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sme2-28.s
#error_output: sme2-28-noarch.l

26
gas/testsuite/gas/aarch64/sme2-28-noarch.l
View File

@ -0,0 +1,26 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z31\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z28\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z0\.s-z3\.s},#32'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z6\.b,{z12\.s-z15\.s},#25'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z31\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z28\.d-z31\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z0\.d-z3\.d},#64'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z25\.h,{z20\.d-z23\.d},#50'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z31\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z28\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z0\.s-z3\.s},#32'
[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z6\.b,{z12\.s-z15\.s},#25'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z31\.b,{z0\.s-z3\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z28\.s-z31\.s},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z0\.s-z3\.s},#32'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z6\.b,{z12\.s-z15\.s},#25'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z31\.h,{z0\.d-z3\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z28\.d-z31\.d},#1'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z0\.d-z3\.d},#64'
[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z25\.h,{z20\.d-z23\.d},#50'

34
gas/testsuite/gas/aarch64/sme2-28.d
View File

@ -0,0 +1,34 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: c17fdc00 sqrshrn z0\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdc1f sqrshrn z31\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdf80 sqrshrn z0\.b, {z28\.s-z31\.s}, #1
[^:]+: c160dc00 sqrshrn z0\.b, {z0\.s-z3\.s}, #32
[^:]+: c167dd86 sqrshrn z6\.b, {z12\.s-z15\.s}, #25
[^:]+: c1ffdc00 sqrshrn z0\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdc1f sqrshrn z31\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdf80 sqrshrn z0\.h, {z28\.d-z31\.d}, #1
[^:]+: c1a0dc00 sqrshrn z0\.h, {z0\.d-z3\.d}, #64
[^:]+: c1aede99 sqrshrn z25\.h, {z20\.d-z23\.d}, #50
[^:]+: c17fdc40 sqrshrun z0\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdc5f sqrshrun z31\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdfc0 sqrshrun z0\.b, {z28\.s-z31\.s}, #1
[^:]+: c160dc40 sqrshrun z0\.b, {z0\.s-z3\.s}, #32
[^:]+: c167ddc6 sqrshrun z6\.b, {z12\.s-z15\.s}, #25
[^:]+: c17fdc20 uqrshrn z0\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdc3f uqrshrn z31\.b, {z0\.s-z3\.s}, #1
[^:]+: c17fdfa0 uqrshrn z0\.b, {z28\.s-z31\.s}, #1
[^:]+: c160dc20 uqrshrn z0\.b, {z0\.s-z3\.s}, #32
[^:]+: c167dda6 uqrshrn z6\.b, {z12\.s-z15\.s}, #25
[^:]+: c1ffdc20 uqrshrn z0\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdc3f uqrshrn z31\.h, {z0\.d-z3\.d}, #1
[^:]+: c1ffdfa0 uqrshrn z0\.h, {z28\.d-z31\.d}, #1
[^:]+: c1a0dc20 uqrshrn z0\.h, {z0\.d-z3\.d}, #64
[^:]+: c1aedeb9 uqrshrn z25\.h, {z20\.d-z23\.d}, #50

29
gas/testsuite/gas/aarch64/sme2-28.s
View File

@ -0,0 +1,29 @@
sqrshrn z0.b, { z0.s - z3.s }, #1
sqrshrn z31.b, { z0.s - z3.s }, #1
sqrshrn z0.b, { z28.s - z31.s }, #1
sqrshrn z0.b, { z0.s - z3.s }, #32
sqrshrn z6.b, { z12.s - z15.s }, #25
sqrshrn z0.h, { z0.d - z3.d }, #1
sqrshrn z31.h, { z0.d - z3.d }, #1
sqrshrn z0.h, { z28.d - z31.d }, #1
sqrshrn z0.h, { z0.d - z3.d }, #64
sqrshrn z25.h, { z20.d - z23.d }, #50
sqrshrun z0.b, { z0.s - z3.s }, #1
sqrshrun z31.b, { z0.s - z3.s }, #1
sqrshrun z0.b, { z28.s - z31.s }, #1
sqrshrun z0.b, { z0.s - z3.s }, #32
sqrshrun z6.b, { z12.s - z15.s }, #25
uqrshrn z0.b, { z0.s - z3.s }, #1
uqrshrn z31.b, { z0.s - z3.s }, #1
uqrshrn z0.b, { z28.s - z31.s }, #1
uqrshrn z0.b, { z0.s - z3.s }, #32
uqrshrn z6.b, { z12.s - z15.s }, #25
uqrshrn z0.h, { z0.d - z3.d }, #1
uqrshrn z31.h, { z0.d - z3.d }, #1
uqrshrn z0.h, { z28.d - z31.d }, #1
uqrshrn z0.h, { z0.d - z3.d }, #64
uqrshrn z25.h, { z20.d - z23.d }, #50

3
include/opcode/aarch64.h
View File

@ -520,6 +520,8 @@ enum aarch64_opnd
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */
AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */
@ -713,6 +715,7 @@ enum aarch64_insn_class
sme_mov,
sme_ldr,
sme_psel,
sme_shift,
sme_size_12_bhs,
sme_size_12_hs,
sme_size_22,

23
opcodes/aarch64-asm-2.c
View File

@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
case 268:
case 270:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 193:
case 194:
case 237:
case 262:
case 263:
case 264:
case 265:
case 267:
case 272:
case 273:
case 269:
case 274:
case 275:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 107:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 108:
case 264:
case 266:
case 268:
return aarch64_ins_none (self, info, code, inst, errors);
case 109:
return aarch64_ins_hint (self, info, code, inst, errors);
@ -886,6 +886,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 184:
case 185:
case 186:
case 250:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 204:
case 205:
@ -919,8 +920,6 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 235:
case 236:
case 249:
case 250:
case 251:
case 252:
case 253:
@ -932,6 +931,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 259:
case 260:
case 261:
case 262:
case 263:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 239:
case 240:
@ -947,9 +948,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 248:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 269:
case 270:
case 249:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 271:
case 272:
case 273:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}

14
opcodes/aarch64-asm.c
View File

@ -1624,6 +1624,19 @@ aarch64_ins_simple_index (const aarch64_operand *self,
return true;
}
/* Insert a plain shift-right immediate, when there is only a single
element size. */
bool
aarch64_ins_plain_shrimm (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
unsigned int base = 1 << get_operand_field_width (self, 0);
insert_field (self->fields[0], code, base - info->imm.value, 0);
return true;
}
/* Miscellaneous encoding functions. */
/* Encode size[0], i.e. bit 22, for
@ -1980,6 +1993,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
0, 2, FLD_SVE_M_14, FLD_size);
break;
case sme_shift:
case sve_index:
case sve_shift_pred:
case sve_shift_unpred:

1
opcodes/aarch64-asm.h
View File

@ -111,6 +111,7 @@ AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30);
AARCH64_DECL_OPD_INSERTER (ins_simple_index);
AARCH64_DECL_OPD_INSERTER (ins_plain_shrimm);
#undef AARCH64_DECL_OPD_INSERTER

1092
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large

17
opcodes/aarch64-dis.c
View File

@ -2157,6 +2157,19 @@ aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info,
info->reglane.index = extract_all_fields_after (self, 1, code);
return true;
}
/* Decode a plain shift-right immediate, when there is only a single
element size. */
bool
aarch64_ext_plain_shrimm (const aarch64_operand *self, aarch64_opnd_info *info,
const aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
unsigned int base = 1 << get_operand_field_width (self, 0);
info->imm.value = base - extract_field (self->fields[0], code, 0);
return true;
}
/* Bitfields that are commonly used to encode certain operands' information
may be partially used as part of the base opcode in some instructions.
@ -3078,6 +3091,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
}
break;
case sme_shift:
i = extract_field (FLD_SVE_tszh, inst->value, 0);
goto sve_shift;
case sme_size_12_bhs:
variant = extract_field (FLD_SME_size_12, inst->value, 0);
if (variant >= 3)

1
opcodes/aarch64-dis.h
View File

@ -135,6 +135,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30);
AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_plain_shrimm);
#undef AARCH64_DECL_OPD_EXTRACTOR

2
opcodes/aarch64-opc-2.c
View File

@ -273,6 +273,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1}, "an indexed SVE vector register"},

12
opcodes/aarch64-opc.c
View File

@ -2924,6 +2924,16 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
case AARCH64_OPND_SME_SHRIMM4:
size = 1 << get_operand_fields_width (get_operand_from_code (type));
if (!value_in_range_p (opnd->imm.value, 1, size))
{
set_imm_out_of_range_error (mismatch_detail, idx, 1, size);
return 0;
}
break;
case AARCH64_OPND_SME_SHRIMM5:
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
@ -4103,6 +4113,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_FBITS:
case AARCH64_OPND_TME_UIMM16:
case AARCH64_OPND_SIMM5:
case AARCH64_OPND_SME_SHRIMM4:
case AARCH64_OPND_SME_SHRIMM5:
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:

22
opcodes/aarch64-tbl.h
View File

@ -1628,6 +1628,10 @@
{ \
QLF2(S_H,S_S), \
}
#define OP_SVE_HSU \
{ \
QLF3(S_H,S_S,NIL), \
}
#define OP_SVE_HU \
{ \
QLF2(S_H,NIL), \
@ -1854,6 +1858,11 @@
QLF3(S_S,P_M,S_H), \
QLF3(S_D,P_M,S_S), \
}
#define OP_SVE_VVU_BH_SD \
{ \
QLF3(S_B,S_S,NIL), \
QLF3(S_H,S_D,NIL), \
}
#define OP_SVE_VVU_HSD_BHS \
{ \
QLF3(S_H,S_B,NIL), \
@ -5623,6 +5632,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("sqdmulh", 0xc120ac00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("sqdmulh", 0xc120b400, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("sqdmulh", 0xc120bc00, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("sqrshr", 0xc1e0d400, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
SME2_INSN ("sqrshr", 0xc120d800, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0),
SME2_INSN ("sqrshrn", 0xc120dc00, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0),
SME2_INSN ("sqrshru", 0xc1f0d400, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
SME2_INSN ("sqrshru", 0xc120d840, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0),
SME2_INSN ("sqrshrun", 0xc120dc40, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0),
SME2_INSN ("srshl", 0xc120a220, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("srshl", 0xc120aa20, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("srshl", 0xc120b220, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
@ -5771,6 +5786,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("uqcvt", 0xc123e020, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
SME2_INSN ("uqcvt", 0xc133e020, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
SME2_INSN ("uqcvtn", 0xc133e060, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
SME2_INSN ("uqrshr", 0xc1e0d420, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0),
SME2_INSN ("uqrshr", 0xc120d820, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0),
SME2_INSN ("uqrshrn", 0xc120dc20, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0),
SME2_INSN ("urshl", 0xc120a221, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
@ -6547,6 +6565,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
"Source scalable predicate register with index ") \
Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \
"a shift-right immediate operand") \
Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \
F(FLD_SVE_tszh,FLD_SVE_imm5b), "a shift-right immediate operand") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \
F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \

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