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* configure.tgt: Add mn10300 to list of mulit-arch targets. * config/mn10300/tm-mn10300.h: Delete file. Move contents ... * mn10300-tdep.c: To here.binutils-2_12-branch
5 changed files with 35 additions and 73 deletions
@ -1,6 +1,4 @@ |
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# Target: Matsushita mn10300 |
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TDEPFILES= mn10300-tdep.o |
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TM_FILE= tm-mn10300.h |
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SIM_OBS = remote-sim.o |
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SIM = ../sim/mn10300/libsim.a |
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/* Parameters for execution on a Matsushita mn10300 processor.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001 |
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Free Software Foundation, Inc. |
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Contributed by Geoffrey Noer <noer@cygnus.com> |
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This file is part of GDB. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, |
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Boston, MA 02111-1307, USA. */ |
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#define GDB_MULTI_ARCH 1 |
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/* The mn10300 is little endian. */ |
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#define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN |
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/* All registers are 32bits (phew!). */ |
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#if !GDB_MULTI_ARCH |
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#define REGISTER_SIZE 4 |
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#define MAX_REGISTER_RAW_SIZE 4 |
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#define NUM_REGS 32 |
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#endif |
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#if !GDB_MULTI_ARCH |
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#define REGISTER_VIRTUAL_TYPE(REG) builtin_type_int |
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#endif |
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#if !GDB_MULTI_ARCH |
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#define REGISTER_BYTE(REG) ((REG) * 4) |
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#define REGISTER_VIRTUAL_SIZE(REG) 4 |
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#define REGISTER_RAW_SIZE(REG) 4 |
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#endif |
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#define D0_REGNUM 0 |
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#define D2_REGNUM 2 |
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#define D3_REGNUM 3 |
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#define A0_REGNUM 4 |
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#define A2_REGNUM 6 |
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#define A3_REGNUM 7 |
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#define MDR_REGNUM 10 |
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#define PSW_REGNUM 11 |
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#define LIR_REGNUM 12 |
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#define LAR_REGNUM 13 |
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#define MDRQ_REGNUM 14 |
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#define E0_REGNUM 15 |
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#define MCRH_REGNUM 26 |
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#define MCRL_REGNUM 27 |
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#define MCVF_REGNUM 28 |
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enum movm_register_bits { |
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movm_exother_bit = 0x01, |
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movm_exreg1_bit = 0x02, |
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movm_exreg0_bit = 0x04, |
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movm_other_bit = 0x08, |
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movm_a3_bit = 0x10, |
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movm_a2_bit = 0x20, |
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movm_d3_bit = 0x40, |
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movm_d2_bit = 0x80 |
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}; |
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