riscv
/
binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

sim: sh: fix various parentheses warnings 

Add parentheses to a bunch of places where the compiler suggests we
do to avoid confusion to most readers.
binutils-2_38-branch
Mike Frysinger 5 years ago
parent
7256320b95
commit
6b015f8977
2 changed files with 11 additions and 11 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 18
      sim/sh/gencode.c
  2. 4
      sim/sh/interp.c

18
sim/sh/gencode.c
View File

@ -1863,7 +1863,7 @@ op ppi_tab[] =
"if (i <= 16)",
" res = Sz << i;",
"else if (i >= 128 - 16)",
" res = (unsigned) Sz >> 128 - i; /* no sign extension */",
" res = (unsigned) Sz >> (128 - i); /* no sign extension */",
"else",
" {",
" RAISE_EXCEPTION (SIGILL);",
@ -1887,7 +1887,7 @@ op ppi_tab[] =
" else",
" {",
" res = Sz << i;",
" res_grd = Sz_grd << i | (unsigned) Sz >> 32 - i;",
" res_grd = Sz_grd << i | (unsigned) Sz >> (32 - i);",
" }",
" res_grd = SEXT (res_grd);",
" carry = res_grd & 1;",
@ -1902,7 +1902,7 @@ op ppi_tab[] =
" }",
" else",
" {",
" res = Sz >> i | Sz_grd << 32 - i;",
" res = Sz >> i | Sz_grd << (32 - i);",
" res_grd = Sz_grd >> i;",
" }",
" carry = Sz >> (i - 1) & 1;",
@ -1973,7 +1973,7 @@ op ppi_tab[] =
"ADD_SUB_GE;",
"DSR &= ~0xf1;\n",
"if (res || res_grd)\n",
" DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n",
" DSR |= greater_equal | (res_grd >> 2 & DSR_MASK_N) | overflow;\n",
"else\n",
" DSR |= DSR_MASK_Z | overflow;\n",
"DSR |= carry;\n",
@ -1992,7 +1992,7 @@ op ppi_tab[] =
"ADD_SUB_GE;",
"DSR &= ~0xf1;\n",
"if (res || res_grd)\n",
" DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n",
" DSR |= greater_equal | (res_grd >> 2 & DSR_MASK_N) | overflow;\n",
"else\n",
" DSR |= DSR_MASK_Z | overflow;\n",
"DSR |= carry;\n",
@ -2148,7 +2148,7 @@ op ppi_tab[] =
"if (Sy <= 16)",
" res = Sx << Sy;",
"else if (Sy >= 128 - 16)",
" res = (unsigned) Sx >> 128 - Sy; /* no sign extension */",
" res = (unsigned) Sx >> (128 - Sy); /* no sign extension */",
"else",
" {",
" RAISE_EXCEPTION (SIGILL);",
@ -2171,7 +2171,7 @@ op ppi_tab[] =
" else",
" {",
" res = Sx << Sy;",
" res_grd = Sx_grd << Sy | (unsigned) Sx >> 32 - Sy;",
" res_grd = Sx_grd << Sy | (unsigned) Sx >> (32 - Sy);",
" }",
" res_grd = SEXT (res_grd);",
" carry = res_grd & 1;",
@ -2186,7 +2186,7 @@ op ppi_tab[] =
" }",
" else",
" {",
" res = Sx >> Sy | Sx_grd << 32 - Sy;",
" res = Sx >> Sy | Sx_grd << (32 - Sy);",
" res_grd = Sx_grd >> Sy;",
" }",
" carry = Sx >> (Sy - 1) & 1;",
@ -3347,7 +3347,7 @@ ppi_gensim (void)
printf (" }\n");
printf (" DSR &= ~0xf1;\n");
printf (" if (res || res_grd)\n");
printf (" DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n");
printf (" DSR |= greater_equal | (res_grd >> 2 & DSR_MASK_N) | overflow;\n");
printf (" else\n");
printf (" DSR |= DSR_MASK_Z | overflow;\n");
printf (" assign_dc:\n");

4
sim/sh/interp.c
View File

@ -195,11 +195,11 @@ do { \
#define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
#define SET_BANKN(EXP) \
do { \
IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
IBNR = (IBNR & 0xfe00) | ((EXP) & 0x1f); \
} while (0)
#define SET_ME(EXP) \
do { \
IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
IBNR = (IBNR & 0x3fff) | (((EXP) & 0x3) << 14); \
} while (0)
#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)

Write Preview
Loading…
Cancel
Save