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aarch64: Add the SME2 CLAMP instructions 

FCLAMP, SCLAMP and UCLAMP share the same format, although FCLAMP
doesn't have a .B form.
users/aburgess/try-core-file-pid0
Richard Sandiford 3 years ago
parent
261f8708db
commit
5f05951e4b
9 changed files with 1306 additions and 827 deletions
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Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 3
      gas/testsuite/gas/aarch64/sme2-22-invalid.d
  2. 27
      gas/testsuite/gas/aarch64/sme2-22-invalid.l
  3. 13
      gas/testsuite/gas/aarch64/sme2-22-invalid.s
  4. 3
      gas/testsuite/gas/aarch64/sme2-22-noarch.d
  5. 111
      gas/testsuite/gas/aarch64/sme2-22-noarch.l
  6. 119
      gas/testsuite/gas/aarch64/sme2-22.d
  7. 131
      gas/testsuite/gas/aarch64/sme2-22.s
  8. 1720
      opcodes/aarch64-dis-2.c
  9. 6
      opcodes/aarch64-tbl.h

3
gas/testsuite/gas/aarch64/sme2-22-invalid.d
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@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: sme2-22-invalid.s
#error_output: sme2-22-invalid.l

27
gas/testsuite/gas/aarch64/sme2-22-invalid.l
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@ -0,0 +1,27 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `fclamp 0,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fclamp {z0\.h-z1\.h},0,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fclamp {z0\.h-z1\.h},z0\.h,0'
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp {z0\.b-z1\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp {z0\.h-z1\.h}, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp {z0\.s-z1\.s}, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp {z0\.d-z1\.d}, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp {z0\.b-z3\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp {z0\.h-z3\.h}, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp {z0\.s-z3\.s}, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp {z0\.d-z3\.d}, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp {z0\.q-z1\.q},z0\.q,z0\.q'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp {z0\.h-z1\.h}, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp {z0\.s-z1\.s}, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp {z0\.d-z1\.d}, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `fclamp {z0\.h-z2\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `fclamp {z1\.h-z2\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `fclamp {z1\.h-z4\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `fclamp {z2\.h-z5\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `fclamp {z3\.h-z6\.h},z0\.h,z0\.h'

13
gas/testsuite/gas/aarch64/sme2-22-invalid.s
View File

@ -0,0 +1,13 @@
fclamp 0, z0.h, z0.h
fclamp { z0.h - z1.h }, 0, z0.h
fclamp { z0.h - z1.h }, z0.h, 0
fclamp { z0.b - z1.b }, z0.b, z0.b
fclamp { z0.b - z3.b }, z0.b, z0.b
fclamp { z0.q - z1.q }, z0.q, z0.q
fclamp { z0.h - z2.h }, z0.h, z0.h
fclamp { z1.h - z2.h }, z0.h, z0.h
fclamp { z1.h - z4.h }, z0.h, z0.h
fclamp { z2.h - z5.h }, z0.h, z0.h
fclamp { z3.h - z6.h }, z0.h, z0.h

3
gas/testsuite/gas/aarch64/sme2-22-noarch.d
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@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sme2-22.s
#error_output: sme2-22-noarch.l

111
gas/testsuite/gas/aarch64/sme2-22-noarch.l
View File

@ -0,0 +1,111 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.h-z1\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z30\.h-z31\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.h-z1\.h},z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.h-z1\.h},z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z8\.h-z9\.h},z26\.h,z4\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.s-z1\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z30\.s-z31\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.s-z1\.s},z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.s-z1\.s},z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z18\.s-z19\.s},z9\.s,z14\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.d-z1\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z30\.d-z31\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.d-z1\.d},z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.d-z1\.d},z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z10\.d-z11\.d},z11\.d,z22\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.h-z3\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z28\.h-z31\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.h-z3\.h},z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.h-z3\.h},z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z20\.h-z23\.h},z15\.h,z17\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.s-z3\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z28\.s-z31\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.s-z3\.s},z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.s-z3\.s},z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z24\.s-z27\.s},z29\.s,z6\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.d-z3\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z28\.d-z31\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.d-z3\.d},z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z0\.d-z3\.d},z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp {z8\.d-z11\.d},z7\.d,z30\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.b-z1\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z30\.b-z31\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.b-z1\.b},z31\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.b-z1\.b},z0\.b,z31\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z2\.b-z3\.b},z21\.b,z9\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.h-z1\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z30\.h-z31\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.h-z1\.h},z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.h-z1\.h},z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z8\.h-z9\.h},z26\.h,z4\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.s-z1\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z30\.s-z31\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.s-z1\.s},z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.s-z1\.s},z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z18\.s-z19\.s},z9\.s,z14\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.d-z1\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z30\.d-z31\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.d-z1\.d},z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.d-z1\.d},z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z10\.d-z11\.d},z11\.d,z22\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.b-z3\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z28\.b-z31\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.b-z3\.b},z31\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.b-z3\.b},z0\.b,z31\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z4\.b-z7\.b},z19\.b,z26\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.h-z3\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z28\.h-z31\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.h-z3\.h},z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.h-z3\.h},z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z20\.h-z23\.h},z15\.h,z17\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.s-z3\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z28\.s-z31\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.s-z3\.s},z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.s-z3\.s},z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z24\.s-z27\.s},z29\.s,z6\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.d-z3\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z28\.d-z31\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.d-z3\.d},z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z0\.d-z3\.d},z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `sclamp {z8\.d-z11\.d},z7\.d,z30\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.b-z1\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z30\.b-z31\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.b-z1\.b},z31\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.b-z1\.b},z0\.b,z31\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z2\.b-z3\.b},z21\.b,z9\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.h-z1\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z30\.h-z31\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.h-z1\.h},z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.h-z1\.h},z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z8\.h-z9\.h},z26\.h,z4\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.s-z1\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z30\.s-z31\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.s-z1\.s},z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.s-z1\.s},z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z18\.s-z19\.s},z9\.s,z14\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.d-z1\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z30\.d-z31\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.d-z1\.d},z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.d-z1\.d},z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z10\.d-z11\.d},z11\.d,z22\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.b-z3\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z28\.b-z31\.b},z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.b-z3\.b},z31\.b,z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.b-z3\.b},z0\.b,z31\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z4\.b-z7\.b},z19\.b,z26\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.h-z3\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z28\.h-z31\.h},z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.h-z3\.h},z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.h-z3\.h},z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z20\.h-z23\.h},z15\.h,z17\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.s-z3\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z28\.s-z31\.s},z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.s-z3\.s},z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.s-z3\.s},z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z24\.s-z27\.s},z29\.s,z6\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.d-z3\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z28\.d-z31\.d},z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.d-z3\.d},z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z0\.d-z3\.d},z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `uclamp {z8\.d-z11\.d},z7\.d,z30\.d'

119
gas/testsuite/gas/aarch64/sme2-22.d
View File

@ -0,0 +1,119 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: c160c000 fclamp {z0\.h-z1\.h}, z0\.h, z0\.h
[^:]+: c160c01e fclamp {z30\.h-z31\.h}, z0\.h, z0\.h
[^:]+: c160c3e0 fclamp {z0\.h-z1\.h}, z31\.h, z0\.h
[^:]+: c17fc000 fclamp {z0\.h-z1\.h}, z0\.h, z31\.h
[^:]+: c164c348 fclamp {z8\.h-z9\.h}, z26\.h, z4\.h
[^:]+: c1a0c000 fclamp {z0\.s-z1\.s}, z0\.s, z0\.s
[^:]+: c1a0c01e fclamp {z30\.s-z31\.s}, z0\.s, z0\.s
[^:]+: c1a0c3e0 fclamp {z0\.s-z1\.s}, z31\.s, z0\.s
[^:]+: c1bfc000 fclamp {z0\.s-z1\.s}, z0\.s, z31\.s
[^:]+: c1aec132 fclamp {z18\.s-z19\.s}, z9\.s, z14\.s
[^:]+: c1e0c000 fclamp {z0\.d-z1\.d}, z0\.d, z0\.d
[^:]+: c1e0c01e fclamp {z30\.d-z31\.d}, z0\.d, z0\.d
[^:]+: c1e0c3e0 fclamp {z0\.d-z1\.d}, z31\.d, z0\.d
[^:]+: c1ffc000 fclamp {z0\.d-z1\.d}, z0\.d, z31\.d
[^:]+: c1f6c16a fclamp {z10\.d-z11\.d}, z11\.d, z22\.d
[^:]+: c160c800 fclamp {z0\.h-z3\.h}, z0\.h, z0\.h
[^:]+: c160c81c fclamp {z28\.h-z31\.h}, z0\.h, z0\.h
[^:]+: c160cbe0 fclamp {z0\.h-z3\.h}, z31\.h, z0\.h
[^:]+: c17fc800 fclamp {z0\.h-z3\.h}, z0\.h, z31\.h
[^:]+: c171c9f4 fclamp {z20\.h-z23\.h}, z15\.h, z17\.h
[^:]+: c1a0c800 fclamp {z0\.s-z3\.s}, z0\.s, z0\.s
[^:]+: c1a0c81c fclamp {z28\.s-z31\.s}, z0\.s, z0\.s
[^:]+: c1a0cbe0 fclamp {z0\.s-z3\.s}, z31\.s, z0\.s
[^:]+: c1bfc800 fclamp {z0\.s-z3\.s}, z0\.s, z31\.s
[^:]+: c1a6cbb8 fclamp {z24\.s-z27\.s}, z29\.s, z6\.s
[^:]+: c1e0c800 fclamp {z0\.d-z3\.d}, z0\.d, z0\.d
[^:]+: c1e0c81c fclamp {z28\.d-z31\.d}, z0\.d, z0\.d
[^:]+: c1e0cbe0 fclamp {z0\.d-z3\.d}, z31\.d, z0\.d
[^:]+: c1ffc800 fclamp {z0\.d-z3\.d}, z0\.d, z31\.d
[^:]+: c1fec8e8 fclamp {z8\.d-z11\.d}, z7\.d, z30\.d
[^:]+: c120c400 sclamp {z0\.b-z1\.b}, z0\.b, z0\.b
[^:]+: c120c41e sclamp {z30\.b-z31\.b}, z0\.b, z0\.b
[^:]+: c120c7e0 sclamp {z0\.b-z1\.b}, z31\.b, z0\.b
[^:]+: c13fc400 sclamp {z0\.b-z1\.b}, z0\.b, z31\.b
[^:]+: c129c6a2 sclamp {z2\.b-z3\.b}, z21\.b, z9\.b
[^:]+: c160c400 sclamp {z0\.h-z1\.h}, z0\.h, z0\.h
[^:]+: c160c41e sclamp {z30\.h-z31\.h}, z0\.h, z0\.h
[^:]+: c160c7e0 sclamp {z0\.h-z1\.h}, z31\.h, z0\.h
[^:]+: c17fc400 sclamp {z0\.h-z1\.h}, z0\.h, z31\.h
[^:]+: c164c748 sclamp {z8\.h-z9\.h}, z26\.h, z4\.h
[^:]+: c1a0c400 sclamp {z0\.s-z1\.s}, z0\.s, z0\.s
[^:]+: c1a0c41e sclamp {z30\.s-z31\.s}, z0\.s, z0\.s
[^:]+: c1a0c7e0 sclamp {z0\.s-z1\.s}, z31\.s, z0\.s
[^:]+: c1bfc400 sclamp {z0\.s-z1\.s}, z0\.s, z31\.s
[^:]+: c1aec532 sclamp {z18\.s-z19\.s}, z9\.s, z14\.s
[^:]+: c1e0c400 sclamp {z0\.d-z1\.d}, z0\.d, z0\.d
[^:]+: c1e0c41e sclamp {z30\.d-z31\.d}, z0\.d, z0\.d
[^:]+: c1e0c7e0 sclamp {z0\.d-z1\.d}, z31\.d, z0\.d
[^:]+: c1ffc400 sclamp {z0\.d-z1\.d}, z0\.d, z31\.d
[^:]+: c1f6c56a sclamp {z10\.d-z11\.d}, z11\.d, z22\.d
[^:]+: c120cc00 sclamp {z0\.b-z3\.b}, z0\.b, z0\.b
[^:]+: c120cc1c sclamp {z28\.b-z31\.b}, z0\.b, z0\.b
[^:]+: c120cfe0 sclamp {z0\.b-z3\.b}, z31\.b, z0\.b
[^:]+: c13fcc00 sclamp {z0\.b-z3\.b}, z0\.b, z31\.b
[^:]+: c13ace64 sclamp {z4\.b-z7\.b}, z19\.b, z26\.b
[^:]+: c160cc00 sclamp {z0\.h-z3\.h}, z0\.h, z0\.h
[^:]+: c160cc1c sclamp {z28\.h-z31\.h}, z0\.h, z0\.h
[^:]+: c160cfe0 sclamp {z0\.h-z3\.h}, z31\.h, z0\.h
[^:]+: c17fcc00 sclamp {z0\.h-z3\.h}, z0\.h, z31\.h
[^:]+: c171cdf4 sclamp {z20\.h-z23\.h}, z15\.h, z17\.h
[^:]+: c1a0cc00 sclamp {z0\.s-z3\.s}, z0\.s, z0\.s
[^:]+: c1a0cc1c sclamp {z28\.s-z31\.s}, z0\.s, z0\.s
[^:]+: c1a0cfe0 sclamp {z0\.s-z3\.s}, z31\.s, z0\.s
[^:]+: c1bfcc00 sclamp {z0\.s-z3\.s}, z0\.s, z31\.s
[^:]+: c1a6cfb8 sclamp {z24\.s-z27\.s}, z29\.s, z6\.s
[^:]+: c1e0cc00 sclamp {z0\.d-z3\.d}, z0\.d, z0\.d
[^:]+: c1e0cc1c sclamp {z28\.d-z31\.d}, z0\.d, z0\.d
[^:]+: c1e0cfe0 sclamp {z0\.d-z3\.d}, z31\.d, z0\.d
[^:]+: c1ffcc00 sclamp {z0\.d-z3\.d}, z0\.d, z31\.d
[^:]+: c1fecce8 sclamp {z8\.d-z11\.d}, z7\.d, z30\.d
[^:]+: c120c401 uclamp {z0\.b-z1\.b}, z0\.b, z0\.b
[^:]+: c120c41f uclamp {z30\.b-z31\.b}, z0\.b, z0\.b
[^:]+: c120c7e1 uclamp {z0\.b-z1\.b}, z31\.b, z0\.b
[^:]+: c13fc401 uclamp {z0\.b-z1\.b}, z0\.b, z31\.b
[^:]+: c129c6a3 uclamp {z2\.b-z3\.b}, z21\.b, z9\.b
[^:]+: c160c401 uclamp {z0\.h-z1\.h}, z0\.h, z0\.h
[^:]+: c160c41f uclamp {z30\.h-z31\.h}, z0\.h, z0\.h
[^:]+: c160c7e1 uclamp {z0\.h-z1\.h}, z31\.h, z0\.h
[^:]+: c17fc401 uclamp {z0\.h-z1\.h}, z0\.h, z31\.h
[^:]+: c164c749 uclamp {z8\.h-z9\.h}, z26\.h, z4\.h
[^:]+: c1a0c401 uclamp {z0\.s-z1\.s}, z0\.s, z0\.s
[^:]+: c1a0c41f uclamp {z30\.s-z31\.s}, z0\.s, z0\.s
[^:]+: c1a0c7e1 uclamp {z0\.s-z1\.s}, z31\.s, z0\.s
[^:]+: c1bfc401 uclamp {z0\.s-z1\.s}, z0\.s, z31\.s
[^:]+: c1aec533 uclamp {z18\.s-z19\.s}, z9\.s, z14\.s
[^:]+: c1e0c401 uclamp {z0\.d-z1\.d}, z0\.d, z0\.d
[^:]+: c1e0c41f uclamp {z30\.d-z31\.d}, z0\.d, z0\.d
[^:]+: c1e0c7e1 uclamp {z0\.d-z1\.d}, z31\.d, z0\.d
[^:]+: c1ffc401 uclamp {z0\.d-z1\.d}, z0\.d, z31\.d
[^:]+: c1f6c56b uclamp {z10\.d-z11\.d}, z11\.d, z22\.d
[^:]+: c120cc01 uclamp {z0\.b-z3\.b}, z0\.b, z0\.b
[^:]+: c120cc1d uclamp {z28\.b-z31\.b}, z0\.b, z0\.b
[^:]+: c120cfe1 uclamp {z0\.b-z3\.b}, z31\.b, z0\.b
[^:]+: c13fcc01 uclamp {z0\.b-z3\.b}, z0\.b, z31\.b
[^:]+: c13ace65 uclamp {z4\.b-z7\.b}, z19\.b, z26\.b
[^:]+: c160cc01 uclamp {z0\.h-z3\.h}, z0\.h, z0\.h
[^:]+: c160cc1d uclamp {z28\.h-z31\.h}, z0\.h, z0\.h
[^:]+: c160cfe1 uclamp {z0\.h-z3\.h}, z31\.h, z0\.h
[^:]+: c17fcc01 uclamp {z0\.h-z3\.h}, z0\.h, z31\.h
[^:]+: c171cdf5 uclamp {z20\.h-z23\.h}, z15\.h, z17\.h
[^:]+: c1a0cc01 uclamp {z0\.s-z3\.s}, z0\.s, z0\.s
[^:]+: c1a0cc1d uclamp {z28\.s-z31\.s}, z0\.s, z0\.s
[^:]+: c1a0cfe1 uclamp {z0\.s-z3\.s}, z31\.s, z0\.s
[^:]+: c1bfcc01 uclamp {z0\.s-z3\.s}, z0\.s, z31\.s
[^:]+: c1a6cfb9 uclamp {z24\.s-z27\.s}, z29\.s, z6\.s
[^:]+: c1e0cc01 uclamp {z0\.d-z3\.d}, z0\.d, z0\.d
[^:]+: c1e0cc1d uclamp {z28\.d-z31\.d}, z0\.d, z0\.d
[^:]+: c1e0cfe1 uclamp {z0\.d-z3\.d}, z31\.d, z0\.d
[^:]+: c1ffcc01 uclamp {z0\.d-z3\.d}, z0\.d, z31\.d
[^:]+: c1fecce9 uclamp {z8\.d-z11\.d}, z7\.d, z30\.d

131
gas/testsuite/gas/aarch64/sme2-22.s
View File

@ -0,0 +1,131 @@
fclamp { z0.h - z1.h }, z0.h, z0.h
fclamp { z30.h - z31.h }, z0.h, z0.h
fclamp { z0.h - z1.h }, z31.h, z0.h
fclamp { z0.h - z1.h }, z0.h, z31.h
fclamp { z8.h - z9.h }, z26.h, z4.h
fclamp { z0.s - z1.s }, z0.s, z0.s
fclamp { z30.s - z31.s }, z0.s, z0.s
fclamp { z0.s - z1.s }, z31.s, z0.s
fclamp { z0.s - z1.s }, z0.s, z31.s
fclamp { z18.s - z19.s }, z9.s, z14.s
fclamp { z0.d - z1.d }, z0.d, z0.d
fclamp { z30.d - z31.d }, z0.d, z0.d
fclamp { z0.d - z1.d }, z31.d, z0.d
fclamp { z0.d - z1.d }, z0.d, z31.d
fclamp { z10.d - z11.d }, z11.d, z22.d
fclamp { z0.h - z3.h }, z0.h, z0.h
fclamp { z28.h - z31.h }, z0.h, z0.h
fclamp { z0.h - z3.h }, z31.h, z0.h
fclamp { z0.h - z3.h }, z0.h, z31.h
fclamp { z20.h - z23.h }, z15.h, z17.h
fclamp { z0.s - z3.s }, z0.s, z0.s
fclamp { z28.s - z31.s }, z0.s, z0.s
fclamp { z0.s - z3.s }, z31.s, z0.s
fclamp { z0.s - z3.s }, z0.s, z31.s
fclamp { z24.s - z27.s }, z29.s, z6.s
fclamp { z0.d - z3.d }, z0.d, z0.d
fclamp { z28.d - z31.d }, z0.d, z0.d
fclamp { z0.d - z3.d }, z31.d, z0.d
fclamp { z0.d - z3.d }, z0.d, z31.d
fclamp { z8.d - z11.d }, z7.d, z30.d
sclamp { z0.b - z1.b }, z0.b, z0.b
sclamp { z30.b - z31.b }, z0.b, z0.b
sclamp { z0.b - z1.b }, z31.b, z0.b
sclamp { z0.b - z1.b }, z0.b, z31.b
sclamp { z2.b - z3.b }, z21.b, z9.b
sclamp { z0.h - z1.h }, z0.h, z0.h
sclamp { z30.h - z31.h }, z0.h, z0.h
sclamp { z0.h - z1.h }, z31.h, z0.h
sclamp { z0.h - z1.h }, z0.h, z31.h
sclamp { z8.h - z9.h }, z26.h, z4.h
sclamp { z0.s - z1.s }, z0.s, z0.s
sclamp { z30.s - z31.s }, z0.s, z0.s
sclamp { z0.s - z1.s }, z31.s, z0.s
sclamp { z0.s - z1.s }, z0.s, z31.s
sclamp { z18.s - z19.s }, z9.s, z14.s
sclamp { z0.d - z1.d }, z0.d, z0.d
sclamp { z30.d - z31.d }, z0.d, z0.d
sclamp { z0.d - z1.d }, z31.d, z0.d
sclamp { z0.d - z1.d }, z0.d, z31.d
sclamp { z10.d - z11.d }, z11.d, z22.d
sclamp { z0.b - z3.b }, z0.b, z0.b
sclamp { z28.b - z31.b }, z0.b, z0.b
sclamp { z0.b - z3.b }, z31.b, z0.b
sclamp { z0.b - z3.b }, z0.b, z31.b
sclamp { z4.b - z7.b }, z19.b, z26.b
sclamp { z0.h - z3.h }, z0.h, z0.h
sclamp { z28.h - z31.h }, z0.h, z0.h
sclamp { z0.h - z3.h }, z31.h, z0.h
sclamp { z0.h - z3.h }, z0.h, z31.h
sclamp { z20.h - z23.h }, z15.h, z17.h
sclamp { z0.s - z3.s }, z0.s, z0.s
sclamp { z28.s - z31.s }, z0.s, z0.s
sclamp { z0.s - z3.s }, z31.s, z0.s
sclamp { z0.s - z3.s }, z0.s, z31.s
sclamp { z24.s - z27.s }, z29.s, z6.s
sclamp { z0.d - z3.d }, z0.d, z0.d
sclamp { z28.d - z31.d }, z0.d, z0.d
sclamp { z0.d - z3.d }, z31.d, z0.d
sclamp { z0.d - z3.d }, z0.d, z31.d
sclamp { z8.d - z11.d }, z7.d, z30.d
uclamp { z0.b - z1.b }, z0.b, z0.b
uclamp { z30.b - z31.b }, z0.b, z0.b
uclamp { z0.b - z1.b }, z31.b, z0.b
uclamp { z0.b - z1.b }, z0.b, z31.b
uclamp { z2.b - z3.b }, z21.b, z9.b
uclamp { z0.h - z1.h }, z0.h, z0.h
uclamp { z30.h - z31.h }, z0.h, z0.h
uclamp { z0.h - z1.h }, z31.h, z0.h
uclamp { z0.h - z1.h }, z0.h, z31.h
uclamp { z8.h - z9.h }, z26.h, z4.h
uclamp { z0.s - z1.s }, z0.s, z0.s
uclamp { z30.s - z31.s }, z0.s, z0.s
uclamp { z0.s - z1.s }, z31.s, z0.s
uclamp { z0.s - z1.s }, z0.s, z31.s
uclamp { z18.s - z19.s }, z9.s, z14.s
uclamp { z0.d - z1.d }, z0.d, z0.d
uclamp { z30.d - z31.d }, z0.d, z0.d
uclamp { z0.d - z1.d }, z31.d, z0.d
uclamp { z0.d - z1.d }, z0.d, z31.d
uclamp { z10.d - z11.d }, z11.d, z22.d
uclamp { z0.b - z3.b }, z0.b, z0.b
uclamp { z28.b - z31.b }, z0.b, z0.b
uclamp { z0.b - z3.b }, z31.b, z0.b
uclamp { z0.b - z3.b }, z0.b, z31.b
uclamp { z4.b - z7.b }, z19.b, z26.b
uclamp { z0.h - z3.h }, z0.h, z0.h
uclamp { z28.h - z31.h }, z0.h, z0.h
uclamp { z0.h - z3.h }, z31.h, z0.h
uclamp { z0.h - z3.h }, z0.h, z31.h
uclamp { z20.h - z23.h }, z15.h, z17.h
uclamp { z0.s - z3.s }, z0.s, z0.s
uclamp { z28.s - z31.s }, z0.s, z0.s
uclamp { z0.s - z3.s }, z31.s, z0.s
uclamp { z0.s - z3.s }, z0.s, z31.s
uclamp { z24.s - z27.s }, z29.s, z6.s
uclamp { z0.d - z3.d }, z0.d, z0.d
uclamp { z28.d - z31.d }, z0.d, z0.d
uclamp { z0.d - z3.d }, z31.d, z0.d
uclamp { z0.d - z3.d }, z0.d, z31.d
uclamp { z8.d - z11.d }, z7.d, z30.d

1720
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large

6
opcodes/aarch64-tbl.h
View File

@ -5377,6 +5377,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("fclamp", 0xc120c000, 0xff20fc01, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
SME2_INSN ("fclamp", 0xc120c800, 0xff20fc03, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
SME2_INSN ("fdot", 0xc1501008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("fdot", 0xc1509008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("fdot", 0xc1201000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
@ -5522,6 +5524,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
SME2_INSN ("sclamp", 0xc120c400, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("sclamp", 0xc120cc00, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("sdot", 0xc1501000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("sdot", 0xc1509000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("sdot", 0xc1601408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
@ -5669,6 +5673,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("suvdot", 0xc1508038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("svdot", 0xc1500020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("svdot", 0xc1508020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("uclamp", 0xc120c401, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("uclamp", 0xc120cc01, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("udot", 0xc1501010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("udot", 0xc1509010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("udot", 0xc1601418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),

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