Fix wording regarding Intel's IA-64 architecture.

27 years ago · 5e35df8e62
2 changed files with 6 additions and 1 deletions
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@ -1,3 +1,8 @@
+2000-02-15  Kevin Buettner  <kevinb@redhat.com>
+
+	* agentexpr.texi: Fix wording regarding Intel's IA-64
+	architecture.
+
 2000-01-16  Tom Tromey  <tromey@cygnus.com>

 	* gdb.texinfo (Breakpoints): Mention breakpoint ranges.
--- a/gdb/doc/agentexpr.texi
+++ b/gdb/doc/agentexpr.texi
@ -798,7 +798,7 @@ When we add side-effects, we should add this.

@item Why does the @code{reg} bytecode take a 16-bit register number?

-Intel's IA64-architecture, Merced, has 128 general-purpose registers,
+Intel's IA-64 architecture has 128 general-purpose registers,
 and 128 floating-point registers, and I'm sure it has some random
 control registers.