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@ -28,6 +28,9 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
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#include "libiberty.h" |
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#include "gdb/remote-sim.h" |
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#include "sim-main.h" |
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#include "sim-base.h" |
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typedef int word; |
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typedef unsigned int uword; |
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@ -39,10 +42,11 @@ FILE *tracefile; |
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instruction. */ |
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#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1) |
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#define EXTRACT_WORD(addr) (((addr)[0] << 24) \ |
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+ ((addr)[1] << 16) \ |
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+ ((addr)[2] << 8) \ |
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+ ((addr)[3])) |
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#define EXTRACT_WORD(addr) \ |
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((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \ |
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+ (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \ |
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+ (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \ |
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+ (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3))) |
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unsigned long |
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moxie_extract_unsigned_integer (addr, len) |
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@ -111,8 +115,6 @@ struct moxie_regset |
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word sregs[256]; /* special registers */ |
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word cc; /* the condition code reg */ |
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int exception; |
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unsigned long msize; |
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unsigned char * memory; |
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unsigned long long insts; /* instruction counter */ |
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}; |
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@ -132,65 +134,20 @@ static char *myname; |
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static SIM_OPEN_KIND sim_kind; |
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static int issue_messages = 0; |
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/* Default to a 16 Mbyte (== 2^23) memory space. */ |
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static int sim_memory_size = 24; |
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#define MEM_SIZE_FLOOR 64 |
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void |
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sim_size (power) |
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int power; |
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sim_size (int s) |
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{ |
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sim_memory_size = power; |
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cpu.asregs.msize = 1 << sim_memory_size; |
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if (cpu.asregs.memory) |
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free (cpu.asregs.memory); |
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/* Watch out for the '0 count' problem. There's probably a better
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way.. e.g., why do we use 64 here? */ |
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if (cpu.asregs.msize < 64) /* Ensure a boundary. */ |
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cpu.asregs.memory = (unsigned char *) calloc (64, (64 + cpu.asregs.msize) / 64); |
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else |
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cpu.asregs.memory = (unsigned char *) calloc (64, cpu.asregs.msize / 64); |
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if (!cpu.asregs.memory) |
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{ |
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if (issue_messages) |
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fprintf (stderr, |
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"Not enough VM for simulation of %d bytes of RAM\n", |
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cpu.asregs.msize); |
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cpu.asregs.msize = 1; |
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cpu.asregs.memory = (unsigned char *) calloc (1, 1); |
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} |
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} |
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static void |
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init_pointers () |
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{ |
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if (cpu.asregs.msize != (1 << sim_memory_size)) |
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sim_size (sim_memory_size); |
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} |
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static void |
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set_initial_gprs () |
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{ |
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int i; |
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long space; |
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unsigned long memsize; |
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init_pointers (); |
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/* Set up machine just out of reset. */ |
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cpu.asregs.regs[PC_REGNO] = 0; |
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memsize = cpu.asregs.msize / (1024 * 1024); |
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if (issue_messages > 1) |
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fprintf (stderr, "Simulated memory of %d Mbytes (0x0 .. 0x%08x)\n", |
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memsize, cpu.asregs.msize - 1); |
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/* Clean out the register contents. */ |
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for (i = 0; i < NUM_MOXIE_REGS; i++) |
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cpu.asregs.regs[i] = 0; |
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@ -207,168 +164,61 @@ interrupt () |
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/* Write a 1 byte value to memory. */ |
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static void INLINE |
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wbat (pc, x, v) |
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word pc, x, v; |
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wbat (sim_cpu *scpu, word pc, word x, word v) |
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{ |
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if (((uword)x) >= cpu.asregs.msize) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "byte write to 0x%x outside memory range\n", x); |
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cpu.asregs.exception = SIGSEGV; |
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} |
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else |
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{ |
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{ |
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unsigned char * p = cpu.asregs.memory + x; |
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*p = v; |
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} |
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} |
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address_word cia = CIA_GET (scpu); |
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sim_core_write_aligned_1 (scpu, cia, write_map, x, v); |
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} |
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/* Write a 2 byte value to memory. */ |
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static void INLINE |
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wsat (pc, x, v) |
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word pc, x, v; |
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wsat (sim_cpu *scpu, word pc, word x, word v) |
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{ |
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if (((uword)x) >= cpu.asregs.msize) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "short word write to 0x%x outside memory range\n", x); |
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cpu.asregs.exception = SIGSEGV; |
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} |
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else |
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{ |
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if ((x & 1) != 0) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "short word write to unaligned memory address: 0x%x\n", x); |
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cpu.asregs.exception = SIGBUS; |
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} |
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{ |
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unsigned char * p = cpu.asregs.memory + x; |
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p[0] = v >> 8; |
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p[1] = v; |
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} |
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} |
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address_word cia = CIA_GET (scpu); |
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sim_core_write_aligned_2 (scpu, cia, write_map, x, v); |
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} |
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/* Write a 4 byte value to memory. */ |
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static void INLINE |
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wlat (pc, x, v) |
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word pc, x, v; |
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wlat (sim_cpu *scpu, word pc, word x, word v) |
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{ |
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if (((uword)x) >= cpu.asregs.msize) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "word write to 0x%x outside memory range\n", x); |
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cpu.asregs.exception = SIGSEGV; |
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} |
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else |
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{ |
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if ((x & 1) != 0) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "word write to unaligned memory address: 0x%x\n", x); |
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cpu.asregs.exception = SIGBUS; |
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} |
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{ |
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unsigned char * p = cpu.asregs.memory + x; |
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p[0] = v >> 24; |
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p[1] = v >> 16; |
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p[2] = v >> 8; |
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p[3] = v; |
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} |
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} |
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address_word cia = CIA_GET (scpu); |
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sim_core_write_aligned_4 (scpu, cia, write_map, x, v); |
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} |
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/* Read 2 bytes from memory. */ |
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static int INLINE |
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rsat (pc, x) |
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word pc, x; |
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rsat (sim_cpu *scpu, word pc, word x) |
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{ |
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if (((uword) x) >= cpu.asregs.msize) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "short word read from 0x%x outside memory range\n", x); |
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cpu.asregs.exception = SIGSEGV; |
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return 0; |
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} |
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else |
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{ |
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if ((x & 1) != 0) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "short word read from unaligned address: 0x%x\n", x); |
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cpu.asregs.exception = SIGBUS; |
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return 0; |
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} |
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{ |
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unsigned char * p = cpu.asregs.memory + x; |
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return (p[0] << 8) | p[1]; |
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} |
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} |
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address_word cia = CIA_GET (scpu); |
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return (sim_core_read_aligned_2 (scpu, cia, read_map, x)); |
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} |
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/* Read 1 byte from memory. */ |
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static int INLINE |
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rbat (pc, x) |
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word pc, x; |
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rbat (sim_cpu *scpu, word pc, word x) |
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{ |
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if (((uword) x) >= cpu.asregs.msize) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "byte read from 0x%x outside memory range\n", x); |
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cpu.asregs.exception = SIGSEGV; |
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return 0; |
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} |
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else |
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{ |
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unsigned char * p = cpu.asregs.memory + x; |
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return *p; |
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} |
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address_word cia = CIA_GET (scpu); |
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return (sim_core_read_aligned_1 (scpu, cia, read_map, x)); |
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} |
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/* Read 4 bytes from memory. */ |
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static int INLINE |
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rlat (pc, x) |
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word pc, x; |
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rlat (sim_cpu *scpu, word pc, word x) |
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{ |
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if (((uword) x) >= cpu.asregs.msize) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "word read from 0x%x outside memory range\n", x); |
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cpu.asregs.exception = SIGSEGV; |
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return 0; |
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} |
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else |
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{ |
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if ((x & 3) != 0) |
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{ |
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if (issue_messages) |
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fprintf (stderr, "word read from unaligned address: 0x%x\n", x); |
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cpu.asregs.exception = SIGBUS; |
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return 0; |
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} |
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{ |
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unsigned char * p = cpu.asregs.memory + x; |
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return (EXTRACT_WORD(p)); |
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} |
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} |
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address_word cia = CIA_GET (scpu); |
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return (sim_core_read_aligned_4 (scpu, cia, read_map, x)); |
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} |
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#define CHECK_FLAG(T,H) if (tflags & T) { hflags |= H; tflags ^= T; } |
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@ -407,12 +257,13 @@ sim_resume (sd, step, siggnal) |
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unsigned long long insts; |
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unsigned short inst; |
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void (* sigsave)(); |
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sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */ |
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address_word cia = CIA_GET (scpu); |
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sigsave = signal (SIGINT, interrupt); |
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cpu.asregs.exception = step ? SIGTRAP: 0; |
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pc = cpu.asregs.regs[PC_REGNO]; |
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insts = cpu.asregs.insts; |
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unsigned char *memory = cpu.asregs.memory; |
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/* Run instructions here. */ |
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do |
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@ -420,7 +271,8 @@ sim_resume (sd, step, siggnal) |
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opc = pc; |
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/* Fetch the instruction at pc. */ |
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inst = (memory[pc] << 8) + memory[pc + 1]; |
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inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8) |
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+ sim_core_read_aligned_1 (scpu, cia, read_map, pc+1); |
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/* Decode instruction. */ |
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if (inst & (1 << 15)) |
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@ -568,7 +420,7 @@ sim_resume (sd, step, siggnal) |
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{ |
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int reg = (inst >> 4) & 0xf; |
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TRACE("ldi.l"); |
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unsigned int val = EXTRACT_WORD(&(memory[pc + 2])); |
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unsigned int val = EXTRACT_WORD(pc+2); |
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cpu.asregs.regs[reg] = val; |
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pc += 4; |
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} |
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@ -583,7 +435,7 @@ sim_resume (sd, step, siggnal) |
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break; |
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case 0x03: /* jsra */ |
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{ |
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unsigned int fn = EXTRACT_WORD(&(memory[pc + 2])); |
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unsigned int fn = EXTRACT_WORD(pc+2); |
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unsigned int sp = cpu.asregs.regs[1]; |
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TRACE("jsra"); |
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/* Save a slot for the static chain. */ |
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@ -591,11 +443,11 @@ sim_resume (sd, step, siggnal) |
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/* Push the return address. */ |
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sp -= 4; |
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wlat (opc, sp, pc + 6); |
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wlat (scpu, opc, sp, pc + 6); |
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/* Push the current frame pointer. */ |
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sp -= 4; |
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wlat (opc, sp, cpu.asregs.regs[0]); |
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wlat (scpu, opc, sp, cpu.asregs.regs[0]); |
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/* Uncache the stack pointer and set the pc and $fp. */ |
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cpu.asregs.regs[1] = sp; |
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@ -610,11 +462,11 @@ sim_resume (sd, step, siggnal) |
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TRACE("ret"); |
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/* Pop the frame pointer. */ |
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cpu.asregs.regs[0] = rlat (opc, sp); |
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cpu.asregs.regs[0] = rlat (scpu, opc, sp); |
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sp += 4; |
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/* Pop the return address. */ |
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pc = rlat (opc, sp) - 2; |
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pc = rlat (scpu, opc, sp) - 2; |
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sp += 4; |
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/* Skip over the static chain slot. */ |
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@ -640,7 +492,7 @@ sim_resume (sd, step, siggnal) |
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int b = inst & 0xf; |
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int sp = cpu.asregs.regs[a] - 4; |
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TRACE("push"); |
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wlat (opc, sp, cpu.asregs.regs[b]); |
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wlat (scpu, opc, sp, cpu.asregs.regs[b]); |
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cpu.asregs.regs[a] = sp; |
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} |
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break; |
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@ -650,25 +502,25 @@ sim_resume (sd, step, siggnal) |
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int b = inst & 0xf; |
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int sp = cpu.asregs.regs[a]; |
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TRACE("pop"); |
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cpu.asregs.regs[b] = rlat (opc, sp); |
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cpu.asregs.regs[b] = rlat (scpu, opc, sp); |
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cpu.asregs.regs[a] = sp + 4; |
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} |
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break; |
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case 0x08: /* lda.l */ |
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{ |
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int reg = (inst >> 4) & 0xf; |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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unsigned int addr = EXTRACT_WORD(pc+2); |
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TRACE("lda.l"); |
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cpu.asregs.regs[reg] = rlat (opc, addr); |
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cpu.asregs.regs[reg] = rlat (scpu, opc, addr); |
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pc += 4; |
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} |
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break; |
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case 0x09: /* sta.l */ |
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{ |
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int reg = (inst >> 4) & 0xf; |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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unsigned int addr = EXTRACT_WORD(pc+2); |
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TRACE("sta.l"); |
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wlat (opc, addr, cpu.asregs.regs[reg]); |
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wlat (scpu, opc, addr, cpu.asregs.regs[reg]); |
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pc += 4; |
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} |
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break; |
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@ -679,7 +531,7 @@ sim_resume (sd, step, siggnal) |
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int xv; |
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TRACE("ld.l"); |
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xv = cpu.asregs.regs[src]; |
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cpu.asregs.regs[dest] = rlat (opc, xv); |
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cpu.asregs.regs[dest] = rlat (scpu, opc, xv); |
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} |
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break; |
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case 0x0b: /* st.l */ |
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@ -687,28 +539,28 @@ sim_resume (sd, step, siggnal) |
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int dest = (inst >> 4) & 0xf; |
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int val = inst & 0xf; |
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TRACE("st.l"); |
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wlat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]); |
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wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]); |
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} |
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break; |
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case 0x0c: /* ldo.l */ |
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{ |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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unsigned int addr = EXTRACT_WORD(pc+2); |
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int a = (inst >> 4) & 0xf; |
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int b = inst & 0xf; |
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TRACE("ldo.l"); |
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addr += cpu.asregs.regs[b]; |
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cpu.asregs.regs[a] = rlat(opc, addr); |
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cpu.asregs.regs[a] = rlat (scpu, opc, addr); |
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pc += 4; |
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} |
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break; |
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case 0x0d: /* sto.l */ |
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{ |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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unsigned int addr = EXTRACT_WORD(pc+2); |
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int a = (inst >> 4) & 0xf; |
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int b = inst & 0xf; |
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TRACE("sto.l"); |
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addr += cpu.asregs.regs[a]; |
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wlat(opc, addr, cpu.asregs.regs[b]); |
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wlat (scpu, opc, addr, cpu.asregs.regs[b]); |
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pc += 4; |
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} |
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break; |
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@ -763,11 +615,11 @@ sim_resume (sd, step, siggnal) |
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/* Push the return address. */ |
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sp -= 4; |
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wlat (opc, sp, pc + 2); |
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wlat (scpu, opc, sp, pc + 2); |
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/* Push the current frame pointer. */ |
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sp -= 4; |
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wlat (opc, sp, cpu.asregs.regs[0]); |
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wlat (scpu, opc, sp, cpu.asregs.regs[0]); |
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/* Uncache the stack pointer and set the fp & pc. */ |
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cpu.asregs.regs[1] = sp; |
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@ -777,7 +629,7 @@ sim_resume (sd, step, siggnal) |
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break; |
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case 0x1a: /* jmpa */ |
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{ |
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unsigned int tgt = EXTRACT_WORD(&memory[pc+2]); |
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unsigned int tgt = EXTRACT_WORD(pc+2); |
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TRACE("jmpa"); |
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pc = tgt - 2; |
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} |
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@ -786,7 +638,7 @@ sim_resume (sd, step, siggnal) |
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{ |
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int reg = (inst >> 4) & 0xf; |
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unsigned int val = EXTRACT_WORD(&(memory[pc + 2])); |
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unsigned int val = EXTRACT_WORD(pc+2); |
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TRACE("ldi.b"); |
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cpu.asregs.regs[reg] = val; |
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pc += 4; |
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@ -799,15 +651,15 @@ sim_resume (sd, step, siggnal) |
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int xv; |
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TRACE("ld.b"); |
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xv = cpu.asregs.regs[src]; |
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cpu.asregs.regs[dest] = rbat (opc, xv); |
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cpu.asregs.regs[dest] = rbat (scpu, opc, xv); |
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} |
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break; |
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case 0x1d: /* lda.b */ |
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{ |
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int reg = (inst >> 4) & 0xf; |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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unsigned int addr = EXTRACT_WORD(pc+2); |
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TRACE("lda.b"); |
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cpu.asregs.regs[reg] = rbat (opc, addr); |
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cpu.asregs.regs[reg] = rbat (scpu, opc, addr); |
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pc += 4; |
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} |
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break; |
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@ -816,15 +668,15 @@ sim_resume (sd, step, siggnal) |
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int dest = (inst >> 4) & 0xf; |
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int val = inst & 0xf; |
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TRACE("st.b"); |
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wbat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]); |
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wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]); |
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|
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} |
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break; |
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case 0x1f: /* sta.b */ |
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{ |
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int reg = (inst >> 4) & 0xf; |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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|
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unsigned int addr = EXTRACT_WORD(pc+2); |
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|
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TRACE("sta.b"); |
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wbat (opc, addr, cpu.asregs.regs[reg]); |
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wbat (scpu, opc, addr, cpu.asregs.regs[reg]); |
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pc += 4; |
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|
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} |
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break; |
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@ -832,7 +684,7 @@ sim_resume (sd, step, siggnal) |
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{ |
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int reg = (inst >> 4) & 0xf; |
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unsigned int val = EXTRACT_WORD(&(memory[pc + 2])); |
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unsigned int val = EXTRACT_WORD(pc+2); |
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|
|
TRACE("ldi.s"); |
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cpu.asregs.regs[reg] = val; |
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|
|
pc += 4; |
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@ -845,15 +697,15 @@ sim_resume (sd, step, siggnal) |
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int xv; |
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TRACE("ld.s"); |
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xv = cpu.asregs.regs[src]; |
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cpu.asregs.regs[dest] = rsat (opc, xv); |
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cpu.asregs.regs[dest] = rsat (scpu, opc, xv); |
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|
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} |
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|
|
break; |
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case 0x22: /* lda.s */ |
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|
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{ |
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|
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int reg = (inst >> 4) & 0xf; |
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unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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|
unsigned int addr = EXTRACT_WORD(pc+2); |
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|
TRACE("lda.s"); |
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cpu.asregs.regs[reg] = rsat (opc, addr); |
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|
cpu.asregs.regs[reg] = rsat (scpu, opc, addr); |
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|
|
pc += 4; |
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|
|
} |
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|
|
break; |
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|
|
@ -862,15 +714,15 @@ sim_resume (sd, step, siggnal) |
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int dest = (inst >> 4) & 0xf; |
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|
|
int val = inst & 0xf; |
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|
|
TRACE("st.s"); |
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|
|
wsat (opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]); |
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|
|
wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]); |
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|
|
} |
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|
|
break; |
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|
|
case 0x24: /* sta.s */ |
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|
|
{ |
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|
|
int reg = (inst >> 4) & 0xf; |
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|
|
unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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|
|
unsigned int addr = EXTRACT_WORD(pc+2); |
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|
|
TRACE("sta.s"); |
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|
wsat (opc, addr, cpu.asregs.regs[reg]); |
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|
wsat (scpu, opc, addr, cpu.asregs.regs[reg]); |
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pc += 4; |
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|
} |
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|
break; |
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@ -984,8 +836,11 @@ sim_resume (sd, step, siggnal) |
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|
break; |
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case 0x30: /* swi */ |
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{ |
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unsigned int inum = EXTRACT_WORD(&memory[pc+2]); |
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|
unsigned int inum = EXTRACT_WORD(pc+2); |
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|
|
TRACE("swi"); |
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|
/* Set the special registers appropriately. */ |
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|
cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */ |
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|
cpu.asregs.sregs[3] = inum; |
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|
switch (inum) |
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{ |
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case 0x1: /* SYS_exit */ |
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@ -995,10 +850,12 @@ sim_resume (sd, step, siggnal) |
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} |
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case 0x2: /* SYS_open */ |
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{ |
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char *fname = &memory[cpu.asregs.regs[2]]; |
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char fname[1024]; |
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|
int mode = (int) convert_target_flags ((unsigned) cpu.asregs.regs[3]); |
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int perm = (int) cpu.asregs.regs[4]; |
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int fd = open (fname, mode, perm); |
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|
|
sim_core_read_buffer (sd, scpu, read_map, fname, |
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|
|
cpu.asregs.regs[2], 1024); |
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|
|
/* FIXME - set errno */ |
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|
cpu.asregs.regs[2] = fd; |
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break; |
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|
@ -1006,17 +863,24 @@ sim_resume (sd, step, siggnal) |
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case 0x4: /* SYS_read */ |
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{ |
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|
|
int fd = cpu.asregs.regs[2]; |
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|
|
char *buf = &memory[cpu.asregs.regs[3]]; |
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|
|
unsigned len = (unsigned) cpu.asregs.regs[4]; |
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|
|
char *buf = malloc (len); |
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|
|
cpu.asregs.regs[2] = read (fd, buf, len); |
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|
|
sim_core_write_buffer (sd, scpu, write_map, buf, |
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|
|
cpu.asregs.regs[3], len); |
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|
|
free (buf); |
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|
|
break; |
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|
|
} |
|
|
|
case 0x5: /* SYS_write */ |
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|
|
{ |
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|
|
char *str = &memory[cpu.asregs.regs[3]]; |
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|
|
char *str; |
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|
|
/* String length is at 0x12($fp) */ |
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|
|
unsigned count, len = (unsigned) cpu.asregs.regs[4]; |
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|
|
str = malloc (len); |
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|
|
sim_core_read_buffer (sd, scpu, read_map, str, |
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|
|
cpu.asregs.regs[3], len); |
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|
|
count = write (cpu.asregs.regs[2], str, len); |
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|
|
free (str); |
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|
|
cpu.asregs.regs[2] = count; |
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|
|
break; |
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|
|
} |
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|
|
@ -1024,18 +888,17 @@ sim_resume (sd, step, siggnal) |
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|
{ |
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|
|
unsigned int handler = cpu.asregs.sregs[1]; |
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|
|
unsigned int sp = cpu.asregs.regs[1]; |
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|
|
cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */ |
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|
|
/* Save a slot for the static chain. */ |
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|
|
sp -= 4; |
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|
|
/* Push the return address. */ |
|
|
|
sp -= 4; |
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|
|
wlat (opc, sp, pc + 6); |
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|
|
wlat (scpu, opc, sp, pc + 6); |
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|
|
/* Push the current frame pointer. */ |
|
|
|
sp -= 4; |
|
|
|
wlat (opc, sp, cpu.asregs.regs[0]); |
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|
|
wlat (scpu, opc, sp, cpu.asregs.regs[0]); |
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|
|
/* Uncache the stack pointer and set the fp & pc. */ |
|
|
|
cpu.asregs.regs[1] = sp; |
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|
|
@ -1095,45 +958,45 @@ sim_resume (sd, step, siggnal) |
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|
|
break; |
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|
|
case 0x36: /* ldo.b */ |
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|
|
{ |
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|
|
unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
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|
|
unsigned int addr = EXTRACT_WORD(pc+2); |
|
|
|
int a = (inst >> 4) & 0xf; |
|
|
|
int b = inst & 0xf; |
|
|
|
TRACE("ldo.b"); |
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|
|
addr += cpu.asregs.regs[b]; |
|
|
|
cpu.asregs.regs[a] = rbat(opc, addr); |
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|
|
cpu.asregs.regs[a] = rbat (scpu, opc, addr); |
|
|
|
pc += 4; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 0x37: /* sto.b */ |
|
|
|
{ |
|
|
|
unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
|
|
|
unsigned int addr = EXTRACT_WORD(pc+2); |
|
|
|
int a = (inst >> 4) & 0xf; |
|
|
|
int b = inst & 0xf; |
|
|
|
TRACE("sto.b"); |
|
|
|
addr += cpu.asregs.regs[a]; |
|
|
|
wbat(opc, addr, cpu.asregs.regs[b]); |
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|
|
wbat (scpu, opc, addr, cpu.asregs.regs[b]); |
|
|
|
pc += 4; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 0x38: /* ldo.s */ |
|
|
|
{ |
|
|
|
unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
|
|
|
unsigned int addr = EXTRACT_WORD(pc+2); |
|
|
|
int a = (inst >> 4) & 0xf; |
|
|
|
int b = inst & 0xf; |
|
|
|
TRACE("ldo.s"); |
|
|
|
addr += cpu.asregs.regs[b]; |
|
|
|
cpu.asregs.regs[a] = rsat(opc, addr); |
|
|
|
cpu.asregs.regs[a] = rsat (scpu, opc, addr); |
|
|
|
pc += 4; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 0x39: /* sto.s */ |
|
|
|
{ |
|
|
|
unsigned int addr = EXTRACT_WORD(&memory[pc+2]); |
|
|
|
unsigned int addr = EXTRACT_WORD(pc+2); |
|
|
|
int a = (inst >> 4) & 0xf; |
|
|
|
int b = inst & 0xf; |
|
|
|
TRACE("sto.s"); |
|
|
|
addr += cpu.asregs.regs[a]; |
|
|
|
wsat(opc, addr, cpu.asregs.regs[b]); |
|
|
|
wsat (scpu, opc, addr, cpu.asregs.regs[b]); |
|
|
|
pc += 4; |
|
|
|
} |
|
|
|
break; |
|
|
|
@ -1164,11 +1027,10 @@ sim_write (sd, addr, buffer, size) |
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|
|
unsigned char * buffer; |
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|
|
int size; |
|
|
|
{ |
|
|
|
int i; |
|
|
|
init_pointers (); |
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|
|
memcpy (& cpu.asregs.memory[addr], buffer, size); |
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|
|
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */ |
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|
|
sim_core_write_buffer (sd, scpu, write_map, buffer, addr, size); |
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|
|
return size; |
|
|
|
} |
|
|
|
|
|
|
|
@ -1179,10 +1041,9 @@ sim_read (sd, addr, buffer, size) |
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|
|
unsigned char * buffer; |
|
|
|
int size; |
|
|
|
{ |
|
|
|
int i; |
|
|
|
init_pointers (); |
|
|
|
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|
|
|
memcpy (buffer, & cpu.asregs.memory[addr], size); |
|
|
|
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */ |
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|
|
sim_core_read_buffer (sd, scpu, read_map, buffer, addr, size); |
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|
|
return size; |
|
|
|
} |
|
|
|
@ -1195,8 +1056,6 @@ sim_store_register (sd, rn, memory, length) |
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|
|
unsigned char * memory; |
|
|
|
int length; |
|
|
|
{ |
|
|
|
init_pointers (); |
|
|
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|
|
if (rn < NUM_MOXIE_REGS && rn >= 0) |
|
|
|
{ |
|
|
|
if (length == 4) |
|
|
|
@ -1221,8 +1080,6 @@ sim_fetch_register (sd, rn, memory, length) |
|
|
|
unsigned char * memory; |
|
|
|
int length; |
|
|
|
{ |
|
|
|
init_pointers (); |
|
|
|
|
|
|
|
if (rn < NUM_MOXIE_REGS && rn >= 0) |
|
|
|
{ |
|
|
|
if (length == 4) |
|
|
|
@ -1301,21 +1158,25 @@ sim_open (kind, cb, abfd, argv) |
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|
|
struct bfd * abfd; |
|
|
|
char ** argv; |
|
|
|
{ |
|
|
|
int osize = sim_memory_size; |
|
|
|
SIM_DESC sd = sim_state_alloc (kind, cb); |
|
|
|
printf ("0x%x 0x%x\n", sd, STATE_MAGIC(sd)); |
|
|
|
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
|
|
|
|
|
|
|
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
|
|
|
return 0; |
|
|
|
|
|
|
|
sim_do_command(sd," memory region 0x00000000,0x4000000") ; |
|
|
|
sim_do_command(sd," memory region 0xE0000000,0x10000") ; |
|
|
|
|
|
|
|
myname = argv[0]; |
|
|
|
callback = cb; |
|
|
|
|
|
|
|
if (kind == SIM_OPEN_STANDALONE) |
|
|
|
issue_messages = 1; |
|
|
|
|
|
|
|
/* Discard and reacquire memory -- start with a clean slate. */ |
|
|
|
sim_size (1); /* small */ |
|
|
|
sim_size (osize); /* and back again */ |
|
|
|
|
|
|
|
set_initial_gprs (); /* Reset the GPR registers. */ |
|
|
|
|
|
|
|
/* Fudge our descriptor for now. */ |
|
|
|
return (SIM_DESC) 1; |
|
|
|
return sd; |
|
|
|
} |
|
|
|
|
|
|
|
void |
|
|
|
@ -1326,6 +1187,35 @@ sim_close (sd, quitting) |
|
|
|
/* nothing to do */ |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
/* Load the device tree blob. */ |
|
|
|
|
|
|
|
static void |
|
|
|
load_dtb (SIM_DESC sd, const char *filename) |
|
|
|
{ |
|
|
|
int size = 0; |
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FILE *f = fopen (filename, "rb"); |
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char *buf; |
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sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */ |
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if (f == NULL) |
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{ |
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printf ("WARNING: ``%s'' could not be opened.\n", filename); |
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return; |
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} |
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fseek (f, 0, SEEK_END); |
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size = ftell(f); |
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fseek (f, 0, SEEK_SET); |
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buf = alloca (size); |
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if (size != fread (buf, 1, size, f)) |
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{ |
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printf ("ERROR: error reading ``%s''.\n", filename); |
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return; |
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} |
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sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size); |
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cpu.asregs.sregs[9] = 0xE0000000; |
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fclose (f); |
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} |
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SIM_RC |
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sim_load (sd, prog, abfd, from_tty) |
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SIM_DESC sd; |
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@ -1389,6 +1279,7 @@ sim_create_inferior (sd, prog_bfd, argv, env) |
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{ |
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char ** avp; |
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int l, argc, i, tp; |
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sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */ |
|
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|
|
|
|
|
/* Set the initial register set. */ |
|
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l = issue_messages; |
|
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|
@ -1412,8 +1303,8 @@ sim_create_inferior (sd, prog_bfd, argv, env) |
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|
0x0000???? zero word |
|
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|
0x0000???? start of data pointed to by argv */ |
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|
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wlat (0, 0, 0); |
|
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wlat (0, 4, argc); |
|
|
|
wlat (scpu, 0, 0, 0); |
|
|
|
wlat (scpu, 0, 4, argc); |
|
|
|
|
|
|
|
/* tp is the offset of our first argv data. */ |
|
|
|
tp = 4 + 4 + argc * 4 + 4; |
|
|
|
@ -1421,14 +1312,17 @@ sim_create_inferior (sd, prog_bfd, argv, env) |
|
|
|
for (i = 0; i < argc; i++) |
|
|
|
{ |
|
|
|
/* Set the argv value. */ |
|
|
|
wlat (0, 4 + 4 + i * 4, tp); |
|
|
|
wlat (scpu, 0, 4 + 4 + i * 4, tp); |
|
|
|
|
|
|
|
/* Store the string. */ |
|
|
|
strcpy (&cpu.asregs.memory[tp], argv[i]); |
|
|
|
sim_core_write_buffer (sd, scpu, write_map, argv[i], |
|
|
|
tp, strlen(argv[i])+1); |
|
|
|
tp += strlen (argv[i]) + 1; |
|
|
|
} |
|
|
|
|
|
|
|
wlat (0, 4 + 4 + i * 4, 0); |
|
|
|
wlat (scpu, 0, 4 + 4 + i * 4, 0); |
|
|
|
|
|
|
|
load_dtb (sd, DTB); |
|
|
|
|
|
|
|
return SIM_RC_OK; |
|
|
|
} |
|
|
|
@ -1446,26 +1340,10 @@ sim_do_command (sd, cmd) |
|
|
|
SIM_DESC sd; |
|
|
|
char * cmd; |
|
|
|
{ |
|
|
|
/* Nothing there yet; it's all an error. */ |
|
|
|
|
|
|
|
if (cmd != NULL) |
|
|
|
{ |
|
|
|
char ** simargv = buildargv (cmd); |
|
|
|
if (strcmp (simargv[0], "verbose") == 0) |
|
|
|
{ |
|
|
|
issue_messages = 2; |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
fprintf (stderr,"Error: \"%s\" is not a valid moxie simulator command.\n", |
|
|
|
if (sim_args_command (sd, cmd) != SIM_RC_OK) |
|
|
|
sim_io_printf (sd, |
|
|
|
"Error: \"%s\" is not a valid moxie simulator command.\n", |
|
|
|
cmd); |
|
|
|
} |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
fprintf (stderr, "moxie sim commands: \n"); |
|
|
|
fprintf (stderr, " verbose\n"); |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
void |
|
|
|
|
Anthony Green
17 years ago