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Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.binutils-2_35-branch
Matthew Malcomson
6 years ago
15 changed files with 1438 additions and 4 deletions
@ -0,0 +1,5 @@ |
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#name: Custom Datapath Extension FP missing (CDE) |
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#source: cde.s |
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#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp7 -I$srcdir/$subdir |
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#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -I$srcdir/$subdir |
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#error_output: cde-missing-fp.l |
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@ -0,0 +1,148 @@ |
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[^ :]+: Assembler messages: |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#2048' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#1920' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#64' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#63' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p7,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q7,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#2048' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#1920' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#64' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#63' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p7,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q7,#0' |
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[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode |
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[^ :]+:[0-9]+: Error: bad instruction `vcx1t p0,q0,#0' |
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[^ :]+:[0-9]+: Error: bad instruction `vcx1at p0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#64' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#60' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#2' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#1' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p7,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q7,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q7,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#64' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#60' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#2' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#1' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p7,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q7,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q7,#0' |
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[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode |
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[^ :]+:[0-9]+: Error: bad instruction `vcx2t p0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: bad instruction `vcx2at p0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#8' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#6' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#1' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p7,q0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q7,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q7,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q7,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#8' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#6' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#1' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p7,q0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q7,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q7,q0,#0' |
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[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q7,#0' |
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[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode |
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[^ :]+:[0-9]+: Error: bad instruction `vcx3t p0,q0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: bad instruction `vcx3at p0,q0,q0,q0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#1920' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#64' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#63' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p7,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s1,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s30,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#1920' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#64' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#63' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p7,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d15,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#1920' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#64' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#63' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p7,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s1,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s30,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#1920' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#64' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#63' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p7,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d15,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#60' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#2' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p7,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s1,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s30,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s1,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s30,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#60' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#2' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p7,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d15,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d15,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#60' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#2' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p7,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s1,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s30,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s1,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s30,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#60' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#2' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p7,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d15,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d15,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#6' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p7,s0,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s1,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s30,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s1,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s30,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s1,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s30,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#6' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p7,d0,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d15,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d15,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d15,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#6' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#1' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p7,s0,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s1,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s30,s0,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s1,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s30,s0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s1,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s30,#0' |
|||
[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#0' |
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[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#6' |
|||
[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#1' |
|||
[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p7,d0,d0,d0,#0' |
|||
[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d15,d0,d0,#0' |
|||
[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d15,d0,#0' |
|||
[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d15,#0' |
|||
@ -0,0 +1,7 @@ |
|||
#name: Custom Datapath Extension MVE missing (CDE) |
|||
#source: cde.s |
|||
#as: -mno-warn-deprecated -march=armv8.1-m.main+cdecp0+cdecp7+fp -I$srcdir/$subdir |
|||
#as: -mno-warn-deprecated -march=armv8.1-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp -I$srcdir/$subdir |
|||
#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp7+fp -I$srcdir/$subdir |
|||
#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp -I$srcdir/$subdir |
|||
#error_output: cde-missing-mve.l |
|||
@ -0,0 +1,57 @@ |
|||
[^ :]+: Assembler messages: |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#2048' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#1920' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#64' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#63' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p7,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q7,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#2048' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#1920' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#64' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#63' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p7,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q7,#0' |
|||
[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode |
|||
[^ :]+:[0-9]+: Error: bad instruction `vcx1t p0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: bad instruction `vcx1at p0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#64' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#60' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#2' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#1' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p7,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q7,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q7,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#64' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#60' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#2' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#1' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p7,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q7,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q7,#0' |
|||
[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode |
|||
[^ :]+:[0-9]+: Error: bad instruction `vcx2t p0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: bad instruction `vcx2at p0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#8' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#6' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#1' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p7,q0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q7,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q7,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q7,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#8' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#6' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#1' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p7,q0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q7,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q7,q0,#0' |
|||
[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q7,#0' |
|||
[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode |
|||
[^ :]+:[0-9]+: Error: bad instruction `vcx3t p0,q0,q0,q0,#0' |
|||
[^ :]+:[0-9]+: Error: bad instruction `vcx3at p0,q0,q0,q0,#0' |
|||
|
|||
@ -0,0 +1,99 @@ |
|||
#name: Custom Datapath Extension (CDE) |
|||
#source: cde-mve-or-neon.s |
|||
#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp7+fp -I$srcdir/$subdir |
|||
#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp -I$srcdir/$subdir |
|||
#objdump: -M force-thumb -dr --show-raw-insn -marmv8-m.main -M coproc0=cde -M coproc7=cde |
|||
#... |
|||
00000000 <\.text>: |
|||
*[0-9a-f]+: ec20 0000 vcx1 p0, s0, #0 |
|||
*[0-9a-f]+: ec2f 0000 vcx1 p0, s0, #1920 |
|||
*[0-9a-f]+: ec20 0080 vcx1 p0, s0, #64 |
|||
*[0-9a-f]+: ec20 003f vcx1 p0, s0, #63 |
|||
*[0-9a-f]+: ec20 0700 vcx1 p7, s0, #0 |
|||
*[0-9a-f]+: ec60 0000 vcx1 p0, s1, #0 |
|||
*[0-9a-f]+: ec20 f000 vcx1 p0, s30, #0 |
|||
*[0-9a-f]+: ed20 0000 vcx1 p0, d0, #0 |
|||
*[0-9a-f]+: ed2f 0000 vcx1 p0, d0, #1920 |
|||
*[0-9a-f]+: ed20 0080 vcx1 p0, d0, #64 |
|||
*[0-9a-f]+: ed20 003f vcx1 p0, d0, #63 |
|||
*[0-9a-f]+: ed20 0700 vcx1 p7, d0, #0 |
|||
*[0-9a-f]+: ed20 f000 vcx1 p0, d15, #0 |
|||
*[0-9a-f]+: fc20 0000 vcx1a p0, s0, #0 |
|||
*[0-9a-f]+: fc2f 0000 vcx1a p0, s0, #1920 |
|||
*[0-9a-f]+: fc20 0080 vcx1a p0, s0, #64 |
|||
*[0-9a-f]+: fc20 003f vcx1a p0, s0, #63 |
|||
*[0-9a-f]+: fc20 0700 vcx1a p7, s0, #0 |
|||
*[0-9a-f]+: fc60 0000 vcx1a p0, s1, #0 |
|||
*[0-9a-f]+: fc20 f000 vcx1a p0, s30, #0 |
|||
*[0-9a-f]+: fd20 0000 vcx1a p0, d0, #0 |
|||
*[0-9a-f]+: fd2f 0000 vcx1a p0, d0, #1920 |
|||
*[0-9a-f]+: fd20 0080 vcx1a p0, d0, #64 |
|||
*[0-9a-f]+: fd20 003f vcx1a p0, d0, #63 |
|||
*[0-9a-f]+: fd20 0700 vcx1a p7, d0, #0 |
|||
*[0-9a-f]+: fd20 f000 vcx1a p0, d15, #0 |
|||
*[0-9a-f]+: ec30 0000 vcx2 p0, s0, s0, #0 |
|||
*[0-9a-f]+: ec3f 0000 vcx2 p0, s0, s0, #60 |
|||
*[0-9a-f]+: ec30 0080 vcx2 p0, s0, s0, #2 |
|||
*[0-9a-f]+: ec30 0010 vcx2 p0, s0, s0, #1 |
|||
*[0-9a-f]+: ec30 0700 vcx2 p7, s0, s0, #0 |
|||
*[0-9a-f]+: ec70 0000 vcx2 p0, s1, s0, #0 |
|||
*[0-9a-f]+: ec30 f000 vcx2 p0, s30, s0, #0 |
|||
*[0-9a-f]+: ec30 0020 vcx2 p0, s0, s1, #0 |
|||
*[0-9a-f]+: ec30 000f vcx2 p0, s0, s30, #0 |
|||
*[0-9a-f]+: ed30 0000 vcx2 p0, d0, d0, #0 |
|||
*[0-9a-f]+: ed3f 0000 vcx2 p0, d0, d0, #60 |
|||
*[0-9a-f]+: ed30 0080 vcx2 p0, d0, d0, #2 |
|||
*[0-9a-f]+: ed30 0010 vcx2 p0, d0, d0, #1 |
|||
*[0-9a-f]+: ed30 0700 vcx2 p7, d0, d0, #0 |
|||
*[0-9a-f]+: ed30 f000 vcx2 p0, d15, d0, #0 |
|||
*[0-9a-f]+: ed30 000f vcx2 p0, d0, d15, #0 |
|||
*[0-9a-f]+: fc30 0000 vcx2a p0, s0, s0, #0 |
|||
*[0-9a-f]+: fc3f 0000 vcx2a p0, s0, s0, #60 |
|||
*[0-9a-f]+: fc30 0080 vcx2a p0, s0, s0, #2 |
|||
*[0-9a-f]+: fc30 0010 vcx2a p0, s0, s0, #1 |
|||
*[0-9a-f]+: fc30 0700 vcx2a p7, s0, s0, #0 |
|||
*[0-9a-f]+: fc70 0000 vcx2a p0, s1, s0, #0 |
|||
*[0-9a-f]+: fc30 f000 vcx2a p0, s30, s0, #0 |
|||
*[0-9a-f]+: fc30 0020 vcx2a p0, s0, s1, #0 |
|||
*[0-9a-f]+: fc30 000f vcx2a p0, s0, s30, #0 |
|||
*[0-9a-f]+: fd30 0000 vcx2a p0, d0, d0, #0 |
|||
*[0-9a-f]+: fd3f 0000 vcx2a p0, d0, d0, #60 |
|||
*[0-9a-f]+: fd30 0080 vcx2a p0, d0, d0, #2 |
|||
*[0-9a-f]+: fd30 0010 vcx2a p0, d0, d0, #1 |
|||
*[0-9a-f]+: fd30 0700 vcx2a p7, d0, d0, #0 |
|||
*[0-9a-f]+: fd30 f000 vcx2a p0, d15, d0, #0 |
|||
*[0-9a-f]+: fd30 000f vcx2a p0, d0, d15, #0 |
|||
*[0-9a-f]+: ec80 0000 vcx3 p0, s0, s0, s0, #0 |
|||
*[0-9a-f]+: ecb0 0000 vcx3 p0, s0, s0, s0, #6 |
|||
*[0-9a-f]+: ec80 0010 vcx3 p0, s0, s0, s0, #1 |
|||
*[0-9a-f]+: ec80 0700 vcx3 p7, s0, s0, s0, #0 |
|||
*[0-9a-f]+: ecc0 0000 vcx3 p0, s1, s0, s0, #0 |
|||
*[0-9a-f]+: ec80 f000 vcx3 p0, s30, s0, s0, #0 |
|||
*[0-9a-f]+: ec80 0080 vcx3 p0, s0, s1, s0, #0 |
|||
*[0-9a-f]+: ec8f 0000 vcx3 p0, s0, s30, s0, #0 |
|||
*[0-9a-f]+: ec80 0020 vcx3 p0, s0, s0, s1, #0 |
|||
*[0-9a-f]+: ec80 000f vcx3 p0, s0, s0, s30, #0 |
|||
*[0-9a-f]+: ed80 0000 vcx3 p0, d0, d0, d0, #0 |
|||
*[0-9a-f]+: edb0 0000 vcx3 p0, d0, d0, d0, #6 |
|||
*[0-9a-f]+: ed80 0010 vcx3 p0, d0, d0, d0, #1 |
|||
*[0-9a-f]+: ed80 0700 vcx3 p7, d0, d0, d0, #0 |
|||
*[0-9a-f]+: ed80 f000 vcx3 p0, d15, d0, d0, #0 |
|||
*[0-9a-f]+: ed8f 0000 vcx3 p0, d0, d15, d0, #0 |
|||
*[0-9a-f]+: ed80 000f vcx3 p0, d0, d0, d15, #0 |
|||
*[0-9a-f]+: fc80 0000 vcx3a p0, s0, s0, s0, #0 |
|||
*[0-9a-f]+: fcb0 0000 vcx3a p0, s0, s0, s0, #6 |
|||
*[0-9a-f]+: fc80 0010 vcx3a p0, s0, s0, s0, #1 |
|||
*[0-9a-f]+: fc80 0700 vcx3a p7, s0, s0, s0, #0 |
|||
*[0-9a-f]+: fcc0 0000 vcx3a p0, s1, s0, s0, #0 |
|||
*[0-9a-f]+: fc80 f000 vcx3a p0, s30, s0, s0, #0 |
|||
*[0-9a-f]+: fc80 0080 vcx3a p0, s0, s1, s0, #0 |
|||
*[0-9a-f]+: fc8f 0000 vcx3a p0, s0, s30, s0, #0 |
|||
*[0-9a-f]+: fc80 0020 vcx3a p0, s0, s0, s1, #0 |
|||
*[0-9a-f]+: fc80 000f vcx3a p0, s0, s0, s30, #0 |
|||
*[0-9a-f]+: fd80 0000 vcx3a p0, d0, d0, d0, #0 |
|||
*[0-9a-f]+: fdb0 0000 vcx3a p0, d0, d0, d0, #6 |
|||
*[0-9a-f]+: fd80 0010 vcx3a p0, d0, d0, d0, #1 |
|||
*[0-9a-f]+: fd80 0700 vcx3a p7, d0, d0, d0, #0 |
|||
*[0-9a-f]+: fd80 f000 vcx3a p0, d15, d0, d0, #0 |
|||
*[0-9a-f]+: fd8f 0000 vcx3a p0, d0, d15, d0, #0 |
|||
*[0-9a-f]+: fd80 000f vcx3a p0, d0, d0, d15, #0 |
|||
@ -0,0 +1,96 @@ |
|||
.syntax unified |
|||
vcx1 p0, s0, #0 |
|||
vcx1 p0, s0, #1920 |
|||
vcx1 p0, s0, #64 |
|||
vcx1 p0, s0, #63 |
|||
vcx1 p7, s0, #0 |
|||
vcx1 p0, s1, #0 |
|||
vcx1 p0, s30, #0 |
|||
vcx1 p0, d0, #0 |
|||
vcx1 p0, d0, #1920 |
|||
vcx1 p0, d0, #64 |
|||
vcx1 p0, d0, #63 |
|||
vcx1 p7, d0, #0 |
|||
vcx1 p0, d15, #0 |
|||
vcx1a p0, s0, #0 |
|||
vcx1a p0, s0, #1920 |
|||
vcx1a p0, s0, #64 |
|||
vcx1a p0, s0, #63 |
|||
vcx1a p7, s0, #0 |
|||
vcx1a p0, s1, #0 |
|||
vcx1a p0, s30, #0 |
|||
vcx1a p0, d0, #0 |
|||
vcx1a p0, d0, #1920 |
|||
vcx1a p0, d0, #64 |
|||
vcx1a p0, d0, #63 |
|||
vcx1a p7, d0, #0 |
|||
vcx1a p0, d15, #0 |
|||
|
|||
vcx2 p0, s0, s0, #0 |
|||
vcx2 p0, s0, s0, #60 |
|||
vcx2 p0, s0, s0, #2 |
|||
vcx2 p0, s0, s0, #1 |
|||
vcx2 p7, s0, s0, #0 |
|||
vcx2 p0, s1, s0, #0 |
|||
vcx2 p0, s30, s0, #0 |
|||
vcx2 p0, s0, s1, #0 |
|||
vcx2 p0, s0, s30, #0 |
|||
vcx2 p0, d0, d0, #0 |
|||
vcx2 p0, d0, d0, #60 |
|||
vcx2 p0, d0, d0, #2 |
|||
vcx2 p0, d0, d0, #1 |
|||
vcx2 p7, d0, d0, #0 |
|||
vcx2 p0, d15, d0, #0 |
|||
vcx2 p0, d0, d15, #0 |
|||
vcx2a p0, s0, s0, #0 |
|||
vcx2a p0, s0, s0, #60 |
|||
vcx2a p0, s0, s0, #2 |
|||
vcx2a p0, s0, s0, #1 |
|||
vcx2a p7, s0, s0, #0 |
|||
vcx2a p0, s1, s0, #0 |
|||
vcx2a p0, s30, s0, #0 |
|||
vcx2a p0, s0, s1, #0 |
|||
vcx2a p0, s0, s30, #0 |
|||
vcx2a p0, d0, d0, #0 |
|||
vcx2a p0, d0, d0, #60 |
|||
vcx2a p0, d0, d0, #2 |
|||
vcx2a p0, d0, d0, #1 |
|||
vcx2a p7, d0, d0, #0 |
|||
vcx2a p0, d15, d0, #0 |
|||
vcx2a p0, d0, d15, #0 |
|||
|
|||
|
|||
vcx3 p0, s0, s0, s0, #0 |
|||
vcx3 p0, s0, s0, s0, #6 |
|||
vcx3 p0, s0, s0, s0, #1 |
|||
vcx3 p7, s0, s0, s0, #0 |
|||
vcx3 p0, s1, s0, s0, #0 |
|||
vcx3 p0, s30, s0, s0, #0 |
|||
vcx3 p0, s0, s1, s0, #0 |
|||
vcx3 p0, s0, s30, s0, #0 |
|||
vcx3 p0, s0, s0, s1, #0 |
|||
vcx3 p0, s0, s0, s30, #0 |
|||
vcx3 p0, d0, d0, d0, #0 |
|||
vcx3 p0, d0, d0, d0, #6 |
|||
vcx3 p0, d0, d0, d0, #1 |
|||
vcx3 p7, d0, d0, d0, #0 |
|||
vcx3 p0, d15, d0, d0, #0 |
|||
vcx3 p0, d0, d15, d0, #0 |
|||
vcx3 p0, d0, d0, d15, #0 |
|||
vcx3a p0, s0, s0, s0, #0 |
|||
vcx3a p0, s0, s0, s0, #6 |
|||
vcx3a p0, s0, s0, s0, #1 |
|||
vcx3a p7, s0, s0, s0, #0 |
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vcx3a p0, s1, s0, s0, #0 |
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vcx3a p0, s30, s0, s0, #0 |
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vcx3a p0, s0, s1, s0, #0 |
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vcx3a p0, s0, s30, s0, #0 |
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vcx3a p0, s0, s0, s1, #0 |
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vcx3a p0, s0, s0, s30, #0 |
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vcx3a p0, d0, d0, d0, #0 |
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vcx3a p0, d0, d0, d0, #6 |
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vcx3a p0, d0, d0, d0, #1 |
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vcx3a p7, d0, d0, d0, #0 |
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vcx3a p0, d15, d0, d0, #0 |
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vcx3a p0, d0, d15, d0, #0 |
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vcx3a p0, d0, d0, d15, #0 |
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@ -0,0 +1,62 @@ |
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.syntax unified |
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|
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vcx1 p0, q0, #0 |
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vcx1 p0, q0, #2048 |
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vcx1 p0, q0, #1920 |
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vcx1 p0, q0, #64 |
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vcx1 p0, q0, #63 |
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vcx1 p7, q0, #0 |
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vcx1 p0, q7, #0 |
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vcx1a p0, q0, #0 |
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vcx1a p0, q0, #2048 |
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vcx1a p0, q0, #1920 |
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vcx1a p0, q0, #64 |
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vcx1a p0, q0, #63 |
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vcx1a p7, q0, #0 |
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vcx1a p0, q7, #0 |
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|
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vptt.i8 eq, q0, q0 |
|||
vcx1t p0, q0, #0 |
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vcx1at p0, q0, #0 |
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|
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vcx2 p0, q0, q0, #0 |
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vcx2 p0, q0, q0, #64 |
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vcx2 p0, q0, q0, #60 |
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vcx2 p0, q0, q0, #2 |
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vcx2 p0, q0, q0, #1 |
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vcx2 p7, q0, q0, #0 |
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vcx2 p0, q7, q0, #0 |
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vcx2 p0, q0, q7, #0 |
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vcx2a p0, q0, q0, #0 |
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vcx2a p0, q0, q0, #64 |
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vcx2a p0, q0, q0, #60 |
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vcx2a p0, q0, q0, #2 |
|||
vcx2a p0, q0, q0, #1 |
|||
vcx2a p7, q0, q0, #0 |
|||
vcx2a p0, q7, q0, #0 |
|||
vcx2a p0, q0, q7, #0 |
|||
|
|||
vptt.i8 eq, q0, q0 |
|||
vcx2t p0, q0, q0, #0 |
|||
vcx2at p0, q0, q0, #0 |
|||
|
|||
vcx3 p0, q0, q0, q0, #0 |
|||
vcx3 p0, q0, q0, q0, #8 |
|||
vcx3 p0, q0, q0, q0, #6 |
|||
vcx3 p0, q0, q0, q0, #1 |
|||
vcx3 p7, q0, q0, q0, #0 |
|||
vcx3 p0, q7, q0, q0, #0 |
|||
vcx3 p0, q0, q7, q0, #0 |
|||
vcx3 p0, q0, q0, q7, #0 |
|||
vcx3a p0, q0, q0, q0, #0 |
|||
vcx3a p0, q0, q0, q0, #8 |
|||
vcx3a p0, q0, q0, q0, #6 |
|||
vcx3a p0, q0, q0, q0, #1 |
|||
vcx3a p7, q0, q0, q0, #0 |
|||
vcx3a p0, q7, q0, q0, #0 |
|||
vcx3a p0, q0, q7, q0, #0 |
|||
vcx3a p0, q0, q0, q7, #0 |
|||
|
|||
vptt.i8 eq, q0, q0 |
|||
vcx3t p0, q0, q0, q0, #0 |
|||
vcx3at p0, q0, q0, q0, #0 |
|||
@ -1,3 +1,36 @@ |
|||
.syntax unified |
|||
|
|||
.include "cde-scalar.s" |
|||
|
|||
# vcx1{a} encoding has the following form |
|||
# 111a110i0d10iiiidddd0pppi1iiiiii (vector form) |
|||
|
|||
# 111a110s0d10iiiidddd0pppi0iiiiii (S/D register form) |
|||
# |
|||
# Variants to test: |
|||
# - immediates that set each set of `i` to ones in turn. |
|||
# - each register set to something non-zero |
|||
# (where each block of register sets is set to all-ones if possible) |
|||
# - coprocessor set to 7 |
|||
|
|||
# vcx2{a} encoding has the following form |
|||
# 111a110i0d11iiiidddd0pppi1mimmmm (vector form) |
|||
# 111a110s0d11iiiidddd0pppi0mimmmm (S/D register form) |
|||
# |
|||
# Variants to test: |
|||
# - immediates that set each set of `i` to ones in turn. |
|||
# - each register set to something non-zero |
|||
# (where each block of register sets is set to all-ones if possible) |
|||
# - coprocessor set to 7 |
|||
|
|||
# vcx3{a} encoding has the following form |
|||
# 111a110i1diinnnndddd0pppn1mimmmm (vector form) |
|||
# 111a110s1diinnnndddd0pppn0mimmmm (S/D register form) |
|||
# |
|||
# Variants to test: |
|||
# - immediates that set each set of `i` to ones in turn. |
|||
# - each register set to something non-zero |
|||
# (where each block of register sets is set to all-ones if possible) |
|||
# - coprocessor set to 7 |
|||
.include "cde-mve.s" |
|||
.include "cde-mve-or-neon.s" |
|||
|
|||
Loading…
Reference in new issue