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gas/testsuite/ 

2008-08-27  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/intel.s: Add tests for fidivr.

	* gas/i386/intel.d: Updated.

opcodes/

2008-08-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Correct fidivr operand size.

	* i386-tbl.h: Regenerated.
binutils-arc-20080908-branch
H.J. Lu 18 years ago
parent
a87af0274f
commit
515c56e780
6 changed files with 19 additions and 2 deletions
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  1. 6
      gas/testsuite/ChangeLog
  2. 2
      gas/testsuite/gas/i386/intel.d
  3. 3
      gas/testsuite/gas/i386/intel.s
  4. 6
      opcodes/ChangeLog
  5. 2
      opcodes/i386-opc.tbl
  6. 2
      opcodes/i386-tbl.h

6
gas/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for fidivr.
* gas/i386/intel.d: Updated.
2008-08-26 Jie Zhang <jie.zhang@analog.com>
* gas/bfin/arith_mode.d: New test.

2
gas/testsuite/gas/i386/intel.d
View File

@ -688,4 +688,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
[ ]*[a-f0-9]+: de 3b fidivr \(%ebx\)
[ ]*[a-f0-9]+: da 3b fidivrl \(%ebx\)
#pass

3
gas/testsuite/gas/i386/intel.s
View File

@ -686,3 +686,6 @@ fsubrp
fsubrp st(3)
fsubrp st(3),st
fsubrp st,st(3)
fidivr word ptr [ebx]
fidivr dword ptr [ebx]

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Correct fidivr operand size.
* i386-tbl.h: Regenerated.
2008-08-24 Alan Modra <amodra@bigpond.net.au>
* configure.in: Update a number of obsolete autoconf macros.

2
opcodes/i386-opc.tbl
View File

@ -698,7 +698,7 @@ fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|U
fdivr, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }

2
opcodes/i386-tbl.h
View File

@ -5120,7 +5120,7 @@ const template i386_optab[] =
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
{ "fdivrp", 2, 0xdef8, None, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

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