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Add an index operand to some of the iq2000 co-processor instructions

binutils-csl-arm-2005q1-branch
Nick Clifton 22 years ago
parent
6f372e19e7
commit
4030fa5ade
11 changed files with 155 additions and 149 deletions
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  1. 8
      cpu/ChangeLog
  2. 25
      cpu/iq2000.cpu
  3. 58
      cpu/iq2000m.cpu
  4. 10
      opcodes/ChangeLog
  5. 26
      opcodes/iq2000-asm.c
  6. 64
      opcodes/iq2000-desc.c
  7. 7
      opcodes/iq2000-desc.h
  8. 6
      opcodes/iq2000-dis.c
  9. 36
      opcodes/iq2000-ibld.c
  10. 60
      opcodes/iq2000-opc.c
  11. 4
      opcodes/iq2000-opc.h

8
cpu/ChangeLog
View File

@ -1,3 +1,11 @@
2004-10-27 Nick Clifton <nickc@redhat.com>
* iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
operand.
* iq2000.cpu (dnop index): Rename to _index to avoid complications
with guile.
2004-08-27 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (cfmovs): Change UNIT attribute to FMALL.

25
cpu/iq2000.cpu
View File

@ -1,24 +1,7 @@
; IQ2000/IQ10 Common CPU description. -*- Scheme -*-
;
; Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Vitesse.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
; Copyright (C) 2000, 2001, 2002 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
(include "simplify.inc")
@ -374,7 +357,7 @@
(dnop maskq10 "iq10 mask" () h-uint f-maskq10)
(dnop maskl "mask left" () h-uint f-maskl)
(dnop count "count" () h-uint f-count)
(dnop index "index" () h-uint f-index)
(dnop _index "index" () h-uint f-index)
(dnop execode "execcode" () h-uint f-excode)
(dnop bytecount "byte count" () h-uint f-bytecount)
(dnop cam-y "cam global opn y" () h-uint f-cam-y)

58
cpu/iq2000m.cpu
View File

@ -1,6 +1,6 @@
; IQ2000-only CPU description. -*- Scheme -*-
;
; Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
; Copyright 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Vitesse.
;
@ -375,14 +375,14 @@
())
(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN)
"pkrlr1 $rt,$count"
(+ OP_COP3 (f-rs 29) rt count)
"pkrlr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 29) rt count _index)
(unimp pkrlr1)
())
(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN)
"pkrlr30 $rt,$count"
(+ OP_COP3 (f-rs 31) rt count)
"pkrlr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 31) rt count _index)
(unimp pkrlr30)
())
@ -393,14 +393,14 @@
())
(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN)
"rbr1 $rt,$count"
(+ OP_COP3 (f-rs 24) rt count)
"rbr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 24) rt count _index)
(unimp rbr1)
())
(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN)
"rbr30 $rt,$count"
(+ OP_COP3 (f-rs 26) rt count)
"rbr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 26) rt count _index)
(unimp rbr30)
())
@ -417,14 +417,14 @@
())
(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN)
"rxr1 $rt,$count"
(+ OP_COP3 (f-rs 28) rt count)
"rxr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 28) rt count _index)
(unimp rxr1)
())
(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN)
"rxr30 $rt,$count"
(+ OP_COP3 (f-rs 30) rt count)
"rxr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 30) rt count _index)
(unimp rxr30)
())
@ -495,26 +495,26 @@
())
(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN)
"wbr1 $rt,$count"
(+ OP_COP3 (f-rs 16) rt count)
"wbr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 16) rt count _index)
(unimp wbr1)
())
(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wbr1u $rt,$count"
(+ OP_COP3 (f-rs 17) rt count)
"wbr1u $rt,$_index,$count"
(+ OP_COP3 (f-rs 17) rt count _index)
(unimp wbr1u)
())
(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN)
"wbr30 $rt,$count"
(+ OP_COP3 (f-rs 18) rt count)
"wbr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 18) rt count _index)
(unimp wbr30)
())
(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wbr30u $rt,$count"
(+ OP_COP3 (f-rs 19) rt count)
"wbr30u $rt,$_index,$count"
(+ OP_COP3 (f-rs 19) rt count _index)
(unimp wbr30u)
())
@ -531,26 +531,26 @@
())
(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN)
"wxr1 $rt,$count"
(+ OP_COP3 (f-rs 20) rt count)
"wxr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 20) rt count _index)
(unimp wxr1)
())
(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wxr1u $rt,$count"
(+ OP_COP3 (f-rs 21) rt count)
"wxr1u $rt,$_index,$count"
(+ OP_COP3 (f-rs 21) rt count _index)
(unimp wxr1u)
())
(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN)
"wxr30 $rt,$count"
(+ OP_COP3 (f-rs 22) rt count)
"wxr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 22) rt count _index)
(unimp wxr30)
())
(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wxr30u $rt,$count"
(+ OP_COP3 (f-rs 23) rt count)
"wxr30u $rt,$_index,$count"
(+ OP_COP3 (f-rs 23) rt count _index)
(unimp wxr30u)
())

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2004-10-27 Nick Clifton <nickc@redhat.com>
* opcodes/iq2000-asm.c: Regenerate.
* opcodes/iq2000-desc.c: Regenerate.
* opcodes/iq2000-desc.h: Regenerate.
* opcodes/iq2000-dis.c: Regenerate.
* opcodes/iq2000-ibld.c: Regenerate.
* opcodes/iq2000-opc.c: Regenerate.
* opcodes/iq2000-opc.h: Regenerate.
2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
* crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,

26
opcodes/iq2000-asm.c
View File

@ -48,16 +48,22 @@ static const char * parse_insn_normal
/* -- assembler routines inserted here. */
/* -- asm.c */
#include "safe-ctype.h"
static int iq2000_cgen_isa_register PARAMS ((const char **));
static const char * parse_jtargq10 PARAMS ((CGEN_CPU_DESC, const char **, int, int, enum cgen_parse_operand_result *, unsigned long *));
static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_mlo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
/* Special check to ensure that instruction exists for given machine */
int
iq2000_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
CGEN_INSN *insn;
const CGEN_INSN *insn;
{
int machs = cd->machs;
@ -88,7 +94,7 @@ static int iq2000_cgen_isa_register (strp)
return 1;
}
}
if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h')
if (**strp == '%' && TOLOWER((*strp)[1]) != 'l' && TOLOWER((*strp)[1]) != 'h')
return 1;
return 0;
}
@ -103,7 +109,6 @@ parse_mimm (cd, strp, opindex, valuep)
long *valuep;
{
const char *errmsg;
long value;
/* Verify this isn't a register */
if (iq2000_cgen_isa_register (strp))
@ -116,7 +121,7 @@ parse_mimm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = (-value) & 0xFFFF0000;
if (x != 0 && x != 0xFFFF0000)
if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (-value & 0xFFFF);
@ -135,7 +140,6 @@ parse_imm (cd, strp, opindex, valuep)
unsigned long *valuep;
{
const char *errmsg;
long value;
if (iq2000_cgen_isa_register (strp))
errmsg = _("immediate value cannot be register");
@ -147,7 +151,7 @@ parse_imm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = value & 0xFFFF0000;
if (x != 0 && x != 0xFFFF0000)
if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (value & 0xFFFF);
@ -163,8 +167,8 @@ parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
int reloc;
enum cgen_parse_operand_result *type_addr;
int reloc ATTRIBUTE_UNUSED;
enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED;
unsigned long *valuep;
{
const char *errmsg;
@ -345,6 +349,9 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND__INDEX, &fields->f_index);
break;
case IQ2000_OPERAND_BASE :
errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs);
break;
@ -385,9 +392,6 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
case IQ2000_OPERAND_EXECODE :
errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode);
break;
case IQ2000_OPERAND_F_INDEX :
errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_F_INDEX, &fields->f_index);
break;
case IQ2000_OPERAND_HI16 :
errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm);
break;

64
opcodes/iq2000-desc.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Copyright 1996-2004 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@ -122,7 +122,7 @@ const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
/* Instruction set variants. */
static const CGEN_ISA iq2000_cgen_isa_table[] = {
{ "iq2000", 32, 32, 23, 32 },
{ "iq2000", 32, 32, 32, 32 },
{ 0, 0, 0, 0, 0 }
};
@ -394,8 +394,8 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] =
{ "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
{ 0, { (1<<MACH_BASE) } } },
/* f-index: index */
{ "f-index", IQ2000_OPERAND_F_INDEX, HW_H_UINT, 8, 9,
/* _index: index */
{ "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
{ 0, { (1<<MACH_BASE) } } },
/* execode: execcode */
@ -1167,14 +1167,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
{ 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
},
/* pkrlr1 $rt,$count */
/* pkrlr1 $rt,$_index,$count */
{
IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 23,
IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* pkrlr30 $rt,$count */
/* pkrlr30 $rt,$_index,$count */
{
IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 23,
IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* rb $rd,$rt */
@ -1182,14 +1182,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
IQ2000_INSN_RB, "rb", "rb", 32,
{ 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
},
/* rbr1 $rt,$count */
/* rbr1 $rt,$_index,$count */
{
IQ2000_INSN_RBR1, "rbr1", "rbr1", 23,
IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* rbr30 $rt,$count */
/* rbr30 $rt,$_index,$count */
{
IQ2000_INSN_RBR30, "rbr30", "rbr30", 23,
IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* rfe */
@ -1202,14 +1202,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
IQ2000_INSN_RX, "rx", "rx", 32,
{ 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
},
/* rxr1 $rt,$count */
/* rxr1 $rt,$_index,$count */
{
IQ2000_INSN_RXR1, "rxr1", "rxr1", 23,
IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* rxr30 $rt,$count */
/* rxr30 $rt,$_index,$count */
{
IQ2000_INSN_RXR30, "rxr30", "rxr30", 23,
IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* sleep */
@ -1267,24 +1267,24 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
IQ2000_INSN_WBU, "wbu", "wbu", 32,
{ 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
},
/* wbr1 $rt,$count */
/* wbr1 $rt,$_index,$count */
{
IQ2000_INSN_WBR1, "wbr1", "wbr1", 23,
IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wbr1u $rt,$count */
/* wbr1u $rt,$_index,$count */
{
IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 23,
IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wbr30 $rt,$count */
/* wbr30 $rt,$_index,$count */
{
IQ2000_INSN_WBR30, "wbr30", "wbr30", 23,
IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wbr30u $rt,$count */
/* wbr30u $rt,$_index,$count */
{
IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 23,
IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wx $rd,$rt */
@ -1297,24 +1297,24 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
IQ2000_INSN_WXU, "wxu", "wxu", 32,
{ 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
},
/* wxr1 $rt,$count */
/* wxr1 $rt,$_index,$count */
{
IQ2000_INSN_WXR1, "wxr1", "wxr1", 23,
IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wxr1u $rt,$count */
/* wxr1u $rt,$_index,$count */
{
IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 23,
IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wxr30 $rt,$count */
/* wxr30 $rt,$_index,$count */
{
IQ2000_INSN_WXR30, "wxr30", "wxr30", 23,
IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* wxr30u $rt,$count */
/* wxr30u $rt,$_index,$count */
{
IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 23,
IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
{ 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
},
/* ldw $rt,$lo16($base) */

7
opcodes/iq2000-desc.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Copyright 1996-2004 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@ -42,7 +42,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define CGEN_INSN_LSB0_P 1
/* Minimum size of any insn (in bytes). */
#define CGEN_MIN_INSN_SIZE 3
#define CGEN_MIN_INSN_SIZE 4
/* Maximum size of any insn (in bytes). */
#define CGEN_MAX_INSN_SIZE 4
@ -255,7 +255,7 @@ typedef enum cgen_operand_type {
, IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT
, IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG
, IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT
, IQ2000_OPERAND_F_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
, IQ2000_OPERAND__INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
, IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z
, IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM
, IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10
@ -296,6 +296,7 @@ extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[];
extern CGEN_KEYWORD iq2000_cgen_opval_gr_names;
extern const CGEN_HW_ENTRY iq2000_cgen_hw_table[];

6
opcodes/iq2000-dis.c
View File

@ -92,6 +92,9 @@ iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
print_normal (cd, info, fields->f_index, 0, pc, length);
break;
case IQ2000_OPERAND_BASE :
print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
break;
@ -128,9 +131,6 @@ iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
case IQ2000_OPERAND_EXECODE :
print_normal (cd, info, fields->f_excode, 0, pc, length);
break;
case IQ2000_OPERAND_F_INDEX :
print_normal (cd, info, fields->f_index, 0, pc, length);
break;
case IQ2000_OPERAND_HI16 :
print_normal (cd, info, fields->f_imm, 0, pc, length);
break;

36
opcodes/iq2000-ibld.c
View File

@ -571,6 +571,9 @@ iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer);
break;
case IQ2000_OPERAND_BASE :
errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer);
break;
@ -607,9 +610,6 @@ iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
case IQ2000_OPERAND_EXECODE :
errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer);
break;
case IQ2000_OPERAND_F_INDEX :
errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer);
break;
case IQ2000_OPERAND_HI16 :
errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
break;
@ -754,6 +754,9 @@ iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index);
break;
case IQ2000_OPERAND_BASE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs);
break;
@ -790,9 +793,6 @@ iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
case IQ2000_OPERAND_EXECODE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode);
break;
case IQ2000_OPERAND_F_INDEX :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index);
break;
case IQ2000_OPERAND_HI16 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
break;
@ -927,6 +927,9 @@ iq2000_cgen_get_int_operand (cd, opindex, fields)
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
value = fields->f_index;
break;
case IQ2000_OPERAND_BASE :
value = fields->f_rs;
break;
@ -963,9 +966,6 @@ iq2000_cgen_get_int_operand (cd, opindex, fields)
case IQ2000_OPERAND_EXECODE :
value = fields->f_excode;
break;
case IQ2000_OPERAND_F_INDEX :
value = fields->f_index;
break;
case IQ2000_OPERAND_HI16 :
value = fields->f_imm;
break;
@ -1041,6 +1041,9 @@ iq2000_cgen_get_vma_operand (cd, opindex, fields)
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
value = fields->f_index;
break;
case IQ2000_OPERAND_BASE :
value = fields->f_rs;
break;
@ -1077,9 +1080,6 @@ iq2000_cgen_get_vma_operand (cd, opindex, fields)
case IQ2000_OPERAND_EXECODE :
value = fields->f_excode;
break;
case IQ2000_OPERAND_F_INDEX :
value = fields->f_index;
break;
case IQ2000_OPERAND_HI16 :
value = fields->f_imm;
break;
@ -1164,6 +1164,9 @@ iq2000_cgen_set_int_operand (cd, opindex, fields, value)
{
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
fields->f_index = value;
break;
case IQ2000_OPERAND_BASE :
fields->f_rs = value;
break;
@ -1200,9 +1203,6 @@ iq2000_cgen_set_int_operand (cd, opindex, fields, value)
case IQ2000_OPERAND_EXECODE :
fields->f_excode = value;
break;
case IQ2000_OPERAND_F_INDEX :
fields->f_index = value;
break;
case IQ2000_OPERAND_HI16 :
fields->f_imm = value;
break;
@ -1275,6 +1275,9 @@ iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
{
switch (opindex)
{
case IQ2000_OPERAND__INDEX :
fields->f_index = value;
break;
case IQ2000_OPERAND_BASE :
fields->f_rs = value;
break;
@ -1311,9 +1314,6 @@ iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
case IQ2000_OPERAND_EXECODE :
fields->f_excode = value;
break;
case IQ2000_OPERAND_F_INDEX :
fields->f_index = value;
break;
case IQ2000_OPERAND_HI16 :
fields->f_imm = value;
break;

60
opcodes/iq2000-opc.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Copyright 1996-2004 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@ -166,7 +166,7 @@ static const CGEN_IFMT ifmt_lulck = {
};
static const CGEN_IFMT ifmt_pkrlr1 = {
23, 23, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { 0 } }
32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { F (F_INDEX) }, { 0 } }
};
static const CGEN_IFMT ifmt_rfe = {
@ -1070,16 +1070,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
& ifmt_chkhdr, { 0x4c200007 }
},
/* pkrlr1 $rt,$count */
/* pkrlr1 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4fa00000 }
},
/* pkrlr30 $rt,$count */
/* pkrlr30 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4fe00000 }
},
/* rb $rd,$rt */
@ -1088,16 +1088,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
& ifmt_chkhdr, { 0x4c200004 }
},
/* rbr1 $rt,$count */
/* rbr1 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4f000000 }
},
/* rbr30 $rt,$count */
/* rbr30 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4f400000 }
},
/* rfe */
@ -1112,16 +1112,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
& ifmt_chkhdr, { 0x4c200006 }
},
/* rxr1 $rt,$count */
/* rxr1 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4f800000 }
},
/* rxr30 $rt,$count */
/* rxr30 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4fc00000 }
},
/* sleep */
@ -1190,28 +1190,28 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
& ifmt_chkhdr, { 0x4c200001 }
},
/* wbr1 $rt,$count */
/* wbr1 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4e000000 }
},
/* wbr1u $rt,$count */
/* wbr1u $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4e200000 }
},
/* wbr30 $rt,$count */
/* wbr30 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4e400000 }
},
/* wbr30u $rt,$count */
/* wbr30u $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4e600000 }
},
/* wx $rd,$rt */
@ -1226,28 +1226,28 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
& ifmt_chkhdr, { 0x4c200003 }
},
/* wxr1 $rt,$count */
/* wxr1 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4e800000 }
},
/* wxr1u $rt,$count */
/* wxr1u $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4ea00000 }
},
/* wxr30 $rt,$count */
/* wxr30 $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4ec00000 }
},
/* wxr30u $rt,$count */
/* wxr30u $rt,$_index,$count */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
{ { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } },
& ifmt_pkrlr1, { 0x4ee00000 }
},
/* ldw $rt,$lo16($base) */

4
opcodes/iq2000-opc.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Copyright 1996-2004 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@ -39,7 +39,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
instructions have same mnemonics but different functionality. */
#define CGEN_VALIDATE_INSN_SUPPORTED
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, CGEN_INSN *insn);
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn);
/* -- asm.c */
/* Enum declaration for iq2000 instruction types. */

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