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Add ColfFire v4 support

cagney_bigcore-20040122-branch
Nick Clifton 23 years ago
parent
8b7d96c1c4
commit
3e60263266
15 changed files with 896 additions and 403 deletions
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  1. 12
      bfd/ChangeLog
  2. 5
      bfd/archures.c
  3. 1
      bfd/bfd-in2.h
  4. 53
      bfd/cpu-m68k.c
  5. 1
      bfd/ieee.c
  6. 8
      gas/ChangeLog
  7. 2
      gas/NEWS
  8. 19
      gas/config/m68k-parse.h
  9. 275
      gas/config/tc-m68k.c
  10. 11
      gas/doc/c-m68k.texi
  11. 5
      include/opcode/ChangeLog
  12. 109
      include/opcode/m68k.h
  13. 6
      opcodes/ChangeLog
  14. 62
      opcodes/m68k-dis.c
  15. 730
      opcodes/m68k-opc.c

12
bfd/ChangeLog
View File

@ -1,3 +1,15 @@
2003-10-21 Thorsten Brehm <brehm@gmx.net>
* archures.c (bfd_default_scan): Add support for mcf528x.
* ieee.c (ieee_write_processor): Likewise.
2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com>
Bernardo Innocenti <bernie@develer.com>
* archures.c: Add MCF528x (MCFv4) support.
* bfd/cpu-m68k.c (arch_info_struct): Likewise.
* bfd-in2.h: Regenerate.
2003-10-20 Andrew Cagney <cagney@redhat.com>
* targets.c: Replace "struct sec" with "struct bfd_section"

5
bfd/archures.c
View File

@ -84,6 +84,7 @@ DESCRIPTION
.#define bfd_mach_mcf5206e 10
.#define bfd_mach_mcf5307 11
.#define bfd_mach_mcf5407 12
.#define bfd_mach_mcf528x 13
. bfd_arch_vax, {* DEC Vax *}
. bfd_arch_i960, {* Intel 960 *}
. {* The order of the following is important.
@ -959,6 +960,10 @@ bfd_default_scan (const bfd_arch_info_type *info, const char *string)
arch = bfd_arch_m68k;
number = bfd_mach_mcf5407;
break;
case 5282:
arch = bfd_arch_m68k;
number = bfd_mach_mcf528x;
break;
case 32000:
arch = bfd_arch_we32k;

1
bfd/bfd-in2.h
View File

@ -1519,6 +1519,7 @@ enum bfd_architecture
#define bfd_mach_mcf5206e 10
#define bfd_mach_mcf5307 11
#define bfd_mach_mcf5407 12
#define bfd_mach_mcf528x 13
bfd_arch_vax, /* DEC Vax */
bfd_arch_i960, /* Intel 960 */
/* The order of the following is important.

53
bfd/cpu-m68k.c
View File

@ -1,23 +1,23 @@
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002
Free Software Foundation, Inc.
Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002,
2003 Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -28,18 +28,19 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
static const bfd_arch_info_type arch_info_struct[] =
{
N(bfd_mach_m68000, "m68k:68000", FALSE, &arch_info_struct[1]),
N(bfd_mach_m68008, "m68k:68008", FALSE, &arch_info_struct[2]),
N(bfd_mach_m68010, "m68k:68010", FALSE, &arch_info_struct[3]),
N(bfd_mach_m68020, "m68k:68020", FALSE, &arch_info_struct[4]),
N(bfd_mach_m68030, "m68k:68030", FALSE, &arch_info_struct[5]),
N(bfd_mach_m68040, "m68k:68040", FALSE, &arch_info_struct[6]),
N(bfd_mach_cpu32, "m68k:cpu32", FALSE, &arch_info_struct[7]),
N(bfd_mach_mcf5200,"m68k:5200", FALSE, &arch_info_struct[8]),
N(bfd_mach_mcf5206e,"m68k:5206e",FALSE, &arch_info_struct[9]),
N(bfd_mach_mcf5307, "m68k:5307", FALSE, &arch_info_struct[10]),
N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]),
N(bfd_mach_m68060, "m68k:68060", FALSE, 0),
N(bfd_mach_m68000, "m68k:68000", FALSE, &arch_info_struct[1]),
N(bfd_mach_m68008, "m68k:68008", FALSE, &arch_info_struct[2]),
N(bfd_mach_m68010, "m68k:68010", FALSE, &arch_info_struct[3]),
N(bfd_mach_m68020, "m68k:68020", FALSE, &arch_info_struct[4]),
N(bfd_mach_m68030, "m68k:68030", FALSE, &arch_info_struct[5]),
N(bfd_mach_m68040, "m68k:68040", FALSE, &arch_info_struct[6]),
N(bfd_mach_cpu32, "m68k:cpu32", FALSE, &arch_info_struct[7]),
N(bfd_mach_mcf5200, "m68k:5200", FALSE, &arch_info_struct[8]),
N(bfd_mach_mcf5206e,"m68k:5206e", FALSE, &arch_info_struct[9]),
N(bfd_mach_mcf5307, "m68k:5307", FALSE, &arch_info_struct[10]),
N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]),
N(bfd_mach_m68060, "m68k:68060", FALSE, &arch_info_struct[12]),
N(bfd_mach_mcf528x, "m68k:528x", FALSE, 0),
};
const bfd_arch_info_type bfd_m68k_arch =

1
bfd/ieee.c
View File

@ -3704,6 +3704,7 @@ ieee_write_processor (abfd)
case bfd_mach_mcf5206e:id = "5206e"; break;
case bfd_mach_mcf5307:id = "5307"; break;
case bfd_mach_mcf5407:id = "5407"; break;
case bfd_mach_mcf528x:id = "5282"; break;
}
if (! ieee_write_id (abfd, id))

8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com>
Bernardo Innocenti <bernie@develer.com>
* config/tc-m68k.c: Add MCF528x (MCFv4) support.
* config/m68k-parse.h: Likewise.
* NEWS: Mention the new support.
* doc/c-m68k.texi: Document new processor selection switch.
2003-10-19 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* config/tc-mips.c (normalize_constant_expr): New function to fix sign

2
gas/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Support for Motorola ColdFire MCF528x added.
* Added --gstabs+ switch to enable the generation of STABS debug format
information with GNU extensions.

19
gas/config/m68k-parse.h
View File

@ -1,6 +1,6 @@
/* m68k-parse.h -- header file for m68k assembler
Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000
Free Software Foundation, Inc.
Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
2003 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
@ -105,14 +105,23 @@ enum m68k_register
TC,
SRP,
URP,
BUSCR, /* 68060 added these */
BUSCR, /* 68060 added these. */
PCR,
ROMBAR, /* mcf5200 added these */
ROMBAR, /* mcf5200 added these. */
RAMBAR0,
RAMBAR1,
MMUBAR, /* mcfv4e added these. */
ROMBAR1, /* mcfv4e added these. */
MPCR, EDRAMBAR, SECMBAR, /* mcfv4e added these. */
PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these. */
PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these. */
PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these. */
MBAR0, MBAR1, /* mcfv4e added these. */
ACR0, ACR1, ACR2, ACR3, /* mcf5200 added these. */
FLASHBAR, RAMBAR, /* mcf528x added these. */
MBAR,
#define last_movec_reg MBAR
/* end of movec ordering constraints */
/* End of movec ordering constraints. */
FPI,
FPS,

275
gas/config/tc-m68k.c
View File

@ -1,7 +1,6 @@
/* tc-m68k.c -- Assemble for the m68k family
Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003
Free Software Foundation, Inc.
2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
@ -168,10 +167,21 @@ static const enum m68k_register m68060_control_regs[] = {
0
};
static const enum m68k_register mcf_control_regs[] = {
CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
RAMBAR0, RAMBAR1, MBAR,
0
};
static const enum m68k_register mcf528x_control_regs[] = {
CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
0
};
static const enum m68k_register mcfv4e_control_regs[] = {
CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
PCR3U0, PCR3L0, PCR3U1, PCR3L1,
0
};
#define cpu32_control_regs m68010_control_regs
static const enum m68k_register *control_regs;
@ -225,13 +235,14 @@ struct m68k_it
reloc[5]; /* Five is enough??? */
};
#define cpu_of_arch(x) ((x) & (m68000up|mcf))
#define cpu_of_arch(x) ((x) & (m68000up | mcf))
#define float_of_arch(x) ((x) & mfloat)
#define mmu_of_arch(x) ((x) & mmmu)
#define arch_coldfire_p(x) (((x) & mcf) != 0)
#define arch_coldfire_p(x) ((x) & mcf)
#define arch_coldfire_v4e_p(x) ((x) & mcfv4e)
/* Macros for determining if cpu supports a specific addressing mode. */
#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e))
static struct m68k_it the_ins; /* The instruction being assembled. */
@ -360,19 +371,21 @@ struct m68k_cpu
static const struct m68k_cpu archs[] =
{
{ m68000, "68000", 0 },
{ m68010, "68010", 0 },
{ m68020, "68020", 0 },
{ m68030, "68030", 0 },
{ m68040, "68040", 0 },
{ m68060, "68060", 0 },
{ cpu32, "cpu32", 0 },
{ m68881, "68881", 0 },
{ m68851, "68851", 0 },
{ mcf5200, "5200", 0 },
{ mcf5206e, "5206e", 0 },
{ mcf5307, "5307", 0},
{ mcf5407, "5407", 0},
{ m68000, "68000", 0 },
{ m68010, "68010", 0 },
{ m68020, "68020", 0 },
{ m68030, "68030", 0 },
{ m68040, "68040", 0 },
{ m68060, "68060", 0 },
{ cpu32, "cpu32", 0 },
{ m68881, "68881", 0 },
{ m68851, "68851", 0 },
{ mcf5200, "5200", 0 },
{ mcf5206e,"5206e", 0 },
{ mcf528x, "528x", 0 },
{ mcf5307, "5307", 0 },
{ mcf5407, "5407", 0 },
{ mcfv4e, "cfv4e", 0 },
/* Aliases (effectively, so far as gas is concerned) for the above
cpus. */
{ m68020, "68k", 1 },
@ -403,6 +416,7 @@ static const struct m68k_cpu archs[] =
{ mcf5200, "5202", 1 },
{ mcf5200, "5204", 1 },
{ mcf5200, "5206", 1 },
{ mcf5407, "cfv4", 1 },
};
static const int n_archs = sizeof (archs) / sizeof (archs[0]);
@ -1498,6 +1512,24 @@ m68k_ip (instring)
losing++;
break;
case 'b':
switch (opP->mode)
{
case IMMED:
case ABSL:
case AREG:
case FPREG:
case CONTROL:
case POST:
case PRE:
case REGLST:
losing++;
break;
default:
break;
}
break;
case 'C':
if (opP->mode != CONTROL || opP->reg != CCR)
losing++;
@ -1702,6 +1734,16 @@ m68k_ip (instring)
losing++;
break;
case 'x':
if (opP->mode != IMMED)
losing++;
else if (opP->disp.exp.X_op != O_constant
|| opP->disp.exp.X_add_number < -1
|| opP->disp.exp.X_add_number > 7
|| opP->disp.exp.X_add_number == 0)
losing++;
break;
/* JF these are out of order. We could put them
in order if we were willing to put up with
bunches of #ifdef m68851s in the code.
@ -1763,6 +1805,25 @@ m68k_ip (instring)
losing++;
break;
case 'w':
switch (opP->mode)
{
case IMMED:
case ABSL:
case AREG:
case DREG:
case FPREG:
case CONTROL:
case POST:
case PRE:
case REGLST:
losing++;
break;
default:
break;
}
break;
case 'X':
if (opP->mode != CONTROL
|| (!(opP->reg >= BAD && opP->reg <= BAD + 7)
@ -1807,6 +1868,18 @@ m68k_ip (instring)
opP->mode = AREG;
break;
case 'y':
if (!(opP->mode == AINDR
|| (opP->mode == DISP && !(opP->reg == PC ||
opP->reg == ZPC))))
losing++;
break;
case 'z':
if (!(opP->mode == AINDR || opP->mode == DISP))
losing++;
break;
default:
abort ();
}
@ -1833,6 +1906,9 @@ m68k_ip (instring)
cp = buf + strlen (buf);
switch (ok_arch)
{
case cfloat:
strcpy (cp, _("ColdFire fpu (cfv4e)"));
break;
case mfloat:
strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
break;
@ -1908,12 +1984,16 @@ m68k_ip (instring)
case '/':
case '<':
case '>':
case 'b':
case 'm':
case 'n':
case 'o':
case 'p':
case 'q':
case 'v':
case 'w':
case 'y':
case 'z':
#ifndef NO_68851
case '|':
#endif
@ -1922,7 +2002,7 @@ m68k_ip (instring)
case IMMED:
tmpreg = 0x3c; /* 7.4 */
if (strchr ("bwl", s[1]))
nextword = get_num (&opP->disp, 80);
nextword = get_num (&opP->disp, 90);
else
nextword = get_num (&opP->disp, 0);
if (isvar (&opP->disp))
@ -2034,7 +2114,7 @@ m68k_ip (instring)
break;
case DISP:
nextword = get_num (&opP->disp, 80);
nextword = get_num (&opP->disp, 90);
if (opP->reg == PC
&& ! isvar (&opP->disp)
@ -2130,9 +2210,9 @@ m68k_ip (instring)
case PRE:
case BASE:
nextword = 0;
baseo = get_num (&opP->disp, 80);
baseo = get_num (&opP->disp, 90);
if (opP->mode == POST || opP->mode == PRE)
outro = get_num (&opP->odisp, 80);
outro = get_num (&opP->odisp, 90);
/* Figure out the `addressing mode'.
Also turn on the BASE_DISABLE bit, if needed. */
if (opP->reg == PC || opP->reg == ZPC)
@ -2175,7 +2255,8 @@ m68k_ip (instring)
if ((opP->index.scale != 1
&& cpu_of_arch (current_architecture) < m68020)
|| (opP->index.scale == 8
&& arch_coldfire_p (current_architecture)))
&& (arch_coldfire_p (current_architecture)
&& !arch_coldfire_v4e_p(current_architecture))))
{
opP->error =
_("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
@ -2380,7 +2461,7 @@ m68k_ip (instring)
break;
case ABSL:
nextword = get_num (&opP->disp, 80);
nextword = get_num (&opP->disp, 90);
switch (opP->disp.size)
{
default:
@ -2456,7 +2537,7 @@ m68k_ip (instring)
break;
case '3':
default:
tmpreg = 80;
tmpreg = 90;
break;
}
tmpreg = get_num (&opP->disp, tmpreg);
@ -2523,7 +2604,7 @@ m68k_ip (instring)
break;
case 'B':
tmpreg = get_num (&opP->disp, 80);
tmpreg = get_num (&opP->disp, 90);
switch (s[1])
{
case 'B':
@ -2643,7 +2724,7 @@ m68k_ip (instring)
case 'd': /* JF this is a kludge. */
install_operand ('s', opP->reg - ADDR);
tmpreg = get_num (&opP->disp, 80);
tmpreg = get_num (&opP->disp, 90);
if (!issword (tmpreg))
{
as_warn (_("Expression out of range, using 0"));
@ -2687,15 +2768,19 @@ m68k_ip (instring)
case TC:
tmpreg = 0x003;
break;
case ACR0:
case ITT0:
tmpreg = 0x004;
break;
case ACR1:
case ITT1:
tmpreg = 0x005;
break;
case ACR2:
case DTT0:
tmpreg = 0x006;
break;
case ACR3:
case DTT1:
tmpreg = 0x007;
break;
@ -2733,15 +2818,67 @@ m68k_ip (instring)
case ROMBAR:
tmpreg = 0xC00;
break;
case ROMBAR1:
tmpreg = 0xC01;
break;
case FLASHBAR:
case RAMBAR0:
tmpreg = 0xC04;
break;
case RAMBAR:
case RAMBAR1:
tmpreg = 0xC05;
break;
case MPCR:
tmpreg = 0xC0C;
break;
case EDRAMBAR:
tmpreg = 0xC0D;
break;
case MBAR0:
case SECMBAR:
tmpreg = 0xC0E;
break;
case MBAR1:
case MBAR:
tmpreg = 0xC0F;
break;
case PCR1U0:
tmpreg = 0xD02;
break;
case PCR1L0:
tmpreg = 0xD03;
break;
case PCR2U0:
tmpreg = 0xD04;
break;
case PCR2L0:
tmpreg = 0xD05;
break;
case PCR3U0:
tmpreg = 0xD06;
break;
case PCR3L0:
tmpreg = 0xD07;
break;
case PCR1L1:
tmpreg = 0xD0A;
break;
case PCR1U1:
tmpreg = 0xD0B;
break;
case PCR2L1:
tmpreg = 0xD0C;
break;
case PCR2U1:
tmpreg = 0xD0D;
break;
case PCR3L1:
tmpreg = 0xD0E;
break;
case PCR3U1:
tmpreg = 0xD0F;
break;
default:
abort ();
}
@ -2990,7 +3127,7 @@ m68k_ip (instring)
case '_': /* used only for move16 absolute 32-bit address. */
if (isvar (&opP->disp))
add_fix ('l', &opP->disp, 0, 0);
tmpreg = get_num (&opP->disp, 80);
tmpreg = get_num (&opP->disp, 90);
addword (tmpreg >> 16);
addword (tmpreg & 0xFFFF);
break;
@ -2999,6 +3136,12 @@ m68k_ip (instring)
opP->reg -= (DATA0L);
opP->reg &= 0x0F; /* remove upper/lower bit. */
break;
case 'x':
tmpreg = get_num (&opP->disp, 80);
if (tmpreg == -1)
tmpreg = 0;
install_operand (s[1], tmpreg);
break;
default:
abort ();
}
@ -3394,10 +3537,10 @@ static const struct init_entry init_table[] =
/* mcf5200 versions of same. The ColdFire programmer's reference
manual indicated that the order is 2,3,0,1, but Ken Rose
<rose@netcom.com> says that 0,1,2,3 is the correct order. */
{ "acr0", ITT0 }, /* Access Control Unit 0. */
{ "acr1", ITT1 }, /* Access Control Unit 1. */
{ "acr2", DTT0 }, /* Access Control Unit 2. */
{ "acr3", DTT1 }, /* Access Control Unit 3. */
{ "acr0", ACR0 }, /* Access Control Unit 0. */
{ "acr1", ACR1 }, /* Access Control Unit 1. */
{ "acr2", ACR2 }, /* Access Control Unit 2. */
{ "acr3", ACR3 }, /* Access Control Unit 3. */
{ "tc", TC }, /* MMU Translation Control Register. */
{ "tcr", TC },
@ -3413,6 +3556,31 @@ static const struct init_entry init_table[] =
{ "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
{ "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
{ "mbar", MBAR }, /* Module Base Address Register. */
{ "mbar0", MBAR0 }, /* mcfv4e registers. */
{ "mbar1", MBAR1 }, /* mcfv4e registers. */
{ "rombar0", ROMBAR }, /* mcfv4e registers. */
{ "rombar1", ROMBAR1 }, /* mcfv4e registers. */
{ "mpcr", MPCR }, /* mcfv4e registers. */
{ "edrambar", EDRAMBAR }, /* mcfv4e registers. */
{ "secmbar", SECMBAR }, /* mcfv4e registers. */
{ "asid", TC }, /* mcfv4e registers. */
{ "mmubar", BUSCR }, /* mcfv4e registers. */
{ "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
{ "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
{ "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
{ "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
{ "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
{ "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
{ "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
{ "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
{ "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
{ "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
{ "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
{ "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
{ "flashbar", FLASHBAR }, /* mcf528x registers. */
{ "rambar", RAMBAR }, /* mcf528x registers. */
/* End of control registers. */
{ "ac", AC },
@ -3970,6 +4138,12 @@ select_control_regs ()
case mcf5407:
control_regs = mcf_control_regs;
break;
case mcf528x:
control_regs = mcf528x_control_regs;
break;
case mcfv4e:
control_regs = mcfv4e_control_regs;
break;
default:
abort ();
}
@ -4808,17 +4982,16 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
aren't OK are an error (what a shock, no?)
0: Everything is OK
10: Absolute 1:8 only
20: Absolute 0:7 only
30: absolute 0:15 only
40: Absolute 0:31 only
50: absolute 0:127 only
10: Absolute 1:8 only
20: Absolute 0:7 only
30: absolute 0:15 only
40: Absolute 0:31 only
50: absolute 0:127 only
55: absolute -64:63 only
60: absolute -128:127 only
70: absolute 0:4095 only
80: No bignums
*/
60: absolute -128:127 only
70: absolute 0:4095 only
80: absolute -1, 1:7 only
90: No bignums. */
static int
get_num (exp, ok)
@ -4881,6 +5054,15 @@ get_num (exp, ok)
offs (exp) = 0;
}
break;
case 80:
if (offs (exp) < -1
|| offs (exp) > 7
|| offs (exp) == 0)
{
as_warn (_("expression out of range: defaulting to 1"));
offs (exp) = 1;
}
break;
default:
break;
}
@ -4888,7 +5070,7 @@ get_num (exp, ok)
else if (exp->exp.X_op == O_big)
{
if (offs (exp) <= 0 /* flonum. */
&& (ok == 80 /* no bignums. */
&& (ok == 90 /* no bignums */
|| (ok > 10 /* Small-int ranges including 0 ok. */
/* If we have a flonum zero, a zero integer should
do as well (e.g., in moveq). */
@ -4916,7 +5098,7 @@ get_num (exp, ok)
}
else
{
if (ok >= 10 && ok <= 70)
if (ok >= 10 && ok <= 80)
{
op (exp) = O_constant;
adds (exp) = 0;
@ -6951,7 +7133,8 @@ md_show_usage (stream)
-l use 1 word for refs to undefined symbols [default 2]\n\
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m528x | -m5307 |\n\
-m5407 | -mcfv4 | -mcfv4e\n\
specify variant of 680X0 architecture [default %s]\n\
-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
target has/lacks floating-point coprocessor\n\

11
gas/doc/c-m68k.texi
View File

@ -1,4 +1,4 @@
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ -165,6 +165,15 @@ Assemble for the 68060.
Assemble for the CPU32 family of chips.
@item -m5200
@item -m5202
@item -m5204
@item -m5206
@item -m5206e
@item -m528x
@item -m5307
@item -m5407
@item -mcfv4
@item -mcfv4e
Assemble for the ColdFire family of chips.
@item -m68881

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com>
Bernardo Innocenti <bernie@develer.com>
* m68k.h: Add MCFv4/MCF5528x support.
2003-10-19 Hans-Peter Nilsson <hp@bitrange.com>
* mmix.h (JMP_INSN_BYTE): Define.

109
include/opcode/m68k.h
View File

@ -1,55 +1,61 @@
/* Opcode table header for m680[01234]0/m6888[12]/m68851.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001
Free Software Foundation, Inc.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
2003 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/* These are used as bit flags for the arch field in the m68k_opcode
structure. */
#define _m68k_undef 0
#define m68000 0x001
#define m68008 m68000 /* synonym for -m68000. otherwise unused. */
#define m68010 0x002
#define m68020 0x004
#define m68030 0x008
#define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;
#define m68000 0x001
#define m68008 m68000 /* Synonym for -m68000. otherwise unused. */
#define m68010 0x002
#define m68020 0x004
#define m68030 0x008
#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
gas will deal with the few differences. */
#define m68040 0x010
/* there is no 68050 */
#define m68060 0x020
#define m68881 0x040
#define m68882 m68881 /* synonym for -m68881. otherwise unused. */
#define m68851 0x080
#define cpu32 0x100 /* e.g., 68332 */
#define mcf5200 0x200
#define m68040 0x010
/* There is no 68050. */
#define m68060 0x020
#define m68881 0x040
#define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
#define m68851 0x080
#define cpu32 0x100 /* e.g., 68332 */
#define mcf5200 0x200
#define mcf5206e 0x400
#define mcf5307 0x800
#define mcf5407 0x1000
/* handy aliases */
#define m68040up (m68040 | m68060)
#define m68030up (m68030 | m68040up)
#define m68020up (m68020 | m68030up)
#define m68010up (m68010 | cpu32 | m68020up)
#define m68000up (m68000 | m68010up)
#define mcf (mcf5200 | mcf5206e | mcf5307 | mcf5407)
#define mcf5307up (mcf5307 | mcf5407)
#define mcf5307 0x800
#define mcf5407 0x1000
#define mcfv4e 0x2000
#define mcf528x 0x4000
/* Handy aliases. */
#define m68040up (m68040 | m68060)
#define m68030up (m68030 | m68040up)
#define m68020up (m68020 | m68030up)
#define m68010up (m68010 | cpu32 | m68020up)
#define m68000up (m68000 | m68010up)
#define mcf (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e)
#define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e)
#define mcf5307up (mcf5307 | mcf5407 | mcfv4e)
#define mcfv4up (mcf5407 | mcfv4e)
#define mcfv4eup (mcfv4e)
#define cfloat (mcfv4e)
#define mfloat (m68881 | m68882 | m68040 | m68060)
#define mmmu (m68851 | m68030 | m68040 | m68060)
@ -93,7 +99,7 @@ struct m68k_opcode_alias
operand; the second, the place it is stored. */
/* Kinds of operands:
Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-
Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
@ -141,7 +147,7 @@ struct m68k_opcode_alias
Possible values:
0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
0x002 CACR Cache Control Register [60, 40, 30, 20]
0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
0x003 TC MMU Translation Control [60, 40]
0x004 ITT0 Instruction Transparent
Translation reg 0 [60, 40]
@ -153,7 +159,7 @@ struct m68k_opcode_alias
Translation reg 1 [60, 40]
0x008 BUSCR Bus Control Register [60]
0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
0x801 VBR Vector Base reg [60, 40, 30, 20, 10]
0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
0x802 CAAR Cache Address Register [ 30, 20]
0x803 MSP Master Stack Pointer [ 40, 30, 20]
0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
@ -165,6 +171,8 @@ struct m68k_opcode_alias
0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
0xC0F MBAR0 RAM Base Address Register 0 [520X]
0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
L Register list of the type d0-d7/a0-a7 etc.
(New! Improved! Can also hold fp0-fp7, as well!)
@ -218,11 +226,14 @@ struct m68k_opcode_alias
coldfire bset/bclr/btst/mulsl/mulul operands:
q (modes 0,2-5)
v (modes 0,2-5,7.0,7.1)
*/
/* For the 68851: */
/*
I didn't use much imagination in choosing the
b (modes 0,2-5,7.2)
w (modes 2-5,7.2)
y (modes 2,5)
z (modes 2,5,7.2)
x mov3q immediate operand. */
/* For the 68851: */
/* I didn't use much imagination in choosing the
following codes, so many of them aren't very
mnemonic. -rab

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com>
Bernardo Innocenti <bernie@develer.com>
* m68k-dis.c: Add MCFv4/MCF5528x support.
* m68k-opc.c: Likewise.
2003-10-10 Dave Brolley <brolley@redhat.com>
* frv-asm.c,frv-desc.c,frv-opc.c: Regenerated.

62
opcodes/m68k-dis.c
View File

@ -1,21 +1,21 @@
/* Print Motorola 68k instructions.
Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
1998, 1999, 2000, 2001, 2002
1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@ -263,6 +263,9 @@ print_insn_m68k (memaddr, info)
case bfd_mach_mcf5200:
arch_mask = mcf5200;
break;
case bfd_mach_mcf528x:
arch_mask = mcf528x;
break;
case bfd_mach_mcf5206e:
arch_mask = mcf5206e;
break;
@ -342,7 +345,7 @@ print_insn_m68k (memaddr, info)
/* Point at first word of argument data,
and at descriptor for first argument. */
p = buffer + 2;
/* Figure out how long the fixed-size portion of the instruction is.
The only place this is stored in the opcode table is
in the arguments--look for arguments which specify fields in the 2nd
@ -406,10 +409,10 @@ print_insn_m68k (memaddr, info)
}
FETCH_DATA (info, p);
d = best->args;
/* We can the operands twice. The first time we don't print anything,
/* We scan the operands twice. The first time we don't print anything,
but look for errors. */
save_p = p;
@ -537,12 +540,16 @@ print_insn_arg (d, buffer, p0, addr, info)
case 'J':
{
/* FIXME: There's a problem here, different m68k processors call the
same address different names. This table can't get it right
because it doesn't know which processor it's disassembling for. */
static const struct { char *name; int value; } names[]
= {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
{"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
{"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
{"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
{"%msp", 0x803}, {"%isp", 0x804},
{"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
/* Should we be calling this psr like we do in case 'Y'? */
{"%mmusr",0x805},
@ -569,6 +576,14 @@ print_insn_arg (d, buffer, p0, addr, info)
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'x':
val = fetch_arg (buffer, place, 3, info);
/* 0 means -1. */
if (val == 0)
val = -1;
(*info->fprintf_func) (info->stream, "#%d", val);
break;
case 'M':
if (place == 'h')
{
@ -724,7 +739,7 @@ print_insn_arg (d, buffer, p0, addr, info)
case 'I':
/* Get coprocessor ID... */
val = fetch_arg (buffer, 'd', 3, info);
if (val != 1) /* Unusual coprocessor ID? */
(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
break;
@ -748,7 +763,10 @@ print_insn_arg (d, buffer, p0, addr, info)
case 'p':
case 'q':
case 'v':
case 'b':
case 'w':
case 'y':
case 'z':
if (place == 'd')
{
val = fetch_arg (buffer, 'x', 6, info);
@ -1023,7 +1041,7 @@ print_insn_arg (d, buffer, p0, addr, info)
{
short is_upper = 0;
int reg = fetch_arg (buffer, place, 5, info);
if (reg & 0x10)
{
is_upper = 1;
@ -1034,7 +1052,7 @@ print_insn_arg (d, buffer, p0, addr, info)
is_upper ? "u" : "l");
}
break;
default:
return -2;
}
@ -1121,7 +1139,7 @@ fetch_arg (buffer, code, bits, info)
val = (buffer[2] << 8) + buffer[3];
val >>= 7;
break;
case '8':
FETCH_DATA (info, buffer + 3);
val = (buffer[2] << 8) + buffer[3];
@ -1138,13 +1156,13 @@ fetch_arg (buffer, code, bits, info)
val = (buffer[1] >> 6);
break;
case 'm':
case 'm':
val = (buffer[1] & 0x40 ? 0x8 : 0)
| ((buffer[0] >> 1) & 0x7)
| (buffer[3] & 0x80 ? 0x10 : 0);
break;
case 'n':
case 'n':
val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
break;

730
opcodes/m68k-opc.c
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