Claudiu Zissulescu
3 years ago
15 changed files with 3091 additions and 3872 deletions
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/* ARC instruction defintions.
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Copyright (C) 2016-2023 Free Software Foundation, Inc. |
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Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
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This file is part of libopcodes. |
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This library is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3, or (at your option) |
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any later version. |
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|
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It is distributed in the hope that it will be useful, but WITHOUT |
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
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License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software Foundation, |
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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/* Common combinations of FLAGS. */ |
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#define FLAGS_NONE { 0 } |
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#define FLAGS_F { C_F } |
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#define FLAGS_CC { C_CC } |
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#define FLAGS_CCF { C_CC, C_F } |
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/* Common combination of arguments. */ |
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#define ARG_NONE { 0 } |
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#define ARG_32BIT_RARBRC { RA, RB, RC } |
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#define ARG_32BIT_ZARBRC { ZA, RB, RC } |
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#define ARG_32BIT_RBRBRC { RB, RBdup, RC } |
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#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } |
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#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } |
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#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } |
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#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } |
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#define ARG_32BIT_RALIMMRC { RA, LIMM, RC } |
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#define ARG_32BIT_RARBLIMM { RA, RB, LIMM } |
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#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC } |
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#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } |
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#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } |
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#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 } |
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#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 } |
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#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 } |
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#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup } |
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#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup } |
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#define ARG_32BIT_RBRC { RB, RC } |
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#define ARG_32BIT_ZARC { ZA, RC } |
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#define ARG_32BIT_RBU6 { RB, UIMM6_20 } |
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#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 } |
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#define ARG_32BIT_RBLIMM { RB, LIMM } |
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#define ARG_32BIT_ZALIMM { ZA, LIMM } |
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/* Macro to generate 2 operand extension instruction. */ |
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#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ |
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{ NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBRC, FL }, \ |
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{ NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZARC, FL }, \ |
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{ NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBU6, FL }, \ |
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{ NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZAU6, FL }, \ |
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{ NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBLIMM, FL }, \ |
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{ NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMM, FL }, |
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#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ |
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EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F) |
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/* Macro to generate 3 operand extesion instruction. */ |
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#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ |
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{ NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RARBRC, FLAGS_F }, \ |
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{ NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZARBRC, FLAGS_F }, \ |
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{ NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBRBRC, FLAGS_CCF }, \ |
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{ NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RARBU6, FLAGS_F }, \ |
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{ NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZARBU6, FLAGS_F }, \ |
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{ NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBRBU6, FLAGS_CCF }, \ |
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{ NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBRBS12, FLAGS_F }, \ |
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{ NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RALIMMRC, FLAGS_F }, \ |
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{ NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RARBLIMM, FLAGS_F }, \ |
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{ NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMRC, FLAGS_F }, \ |
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{ NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZARBLIMM, FLAGS_F }, \ |
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{ NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \ |
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{ NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ |
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{ NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RALIMMU6, FLAGS_F }, \ |
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{ NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMU6, FLAGS_F }, \ |
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{ NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \ |
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{ NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMS12, FLAGS_F }, \ |
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{ NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_RALIMMLIMM, FLAGS_F }, \ |
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{ NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \ |
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{ NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \ |
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ARG_32BIT_ZALIMMLIMM, FLAGS_CCF }, |
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/* Extension instruction declarations. */ |
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EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43) |
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EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44) |
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EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45) |
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EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42) |
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EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43) |
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@ -1,125 +0,0 @@ |
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/* ARC flag class defintions. |
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Copyright (C) 2023 Free Software Foundation, Inc. |
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Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
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Refactored by Cupertino Miranda (cmiranda@synopsys.com) |
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This file is part of libopcodes. |
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|
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This library is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3, or (at your option) |
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any later version. |
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|
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It is distributed in the hope that it will be useful, but WITHOUT |
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
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License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software Foundation, |
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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FLAG_CLASS(EMPTY, F_CLASS_NONE, 0, 0, F_NULL) |
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FLAG_CLASS(CC_EQ, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_EQUAL) |
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FLAG_CLASS(CC_GE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_GE) |
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FLAG_CLASS(CC_GT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_GT) |
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FLAG_CLASS(CC_HI, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_HI) |
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FLAG_CLASS(CC_HS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTCARRY) |
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FLAG_CLASS(CC_LE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LE) |
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FLAG_CLASS(CC_LO, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_CARRY) |
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FLAG_CLASS(CC_LS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LS) |
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FLAG_CLASS(CC_LT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LT) |
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FLAG_CLASS(CC_NE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTEQUAL) |
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FLAG_CLASS(AA_AB, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AB3) |
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FLAG_CLASS(AA_AW, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AW3) |
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FLAG_CLASS(ZZ_D, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZED) |
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FLAG_CLASS(ZZ_L, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEL) |
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FLAG_CLASS(ZZ_W, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEW) |
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FLAG_CLASS(ZZ_H, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_H1) |
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FLAG_CLASS(ZZ_B, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEB1) |
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FLAG_CLASS(CC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, 0, 0, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T) |
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FLAG_CLASS(AA_ADDR3, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3) |
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FLAG_CLASS(AA27, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3) |
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FLAG_CLASS(AS27, F_CLASS_OPTIONAL, 0, 0, F_AS3) |
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FLAG_CLASS(AA_ADDR9, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9) |
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FLAG_CLASS(AA21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9) |
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FLAG_CLASS(AAB21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9) |
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FLAG_CLASS(AA_ADDR22, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22) |
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FLAG_CLASS(AA8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22) |
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FLAG_CLASS(AAB8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22) |
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FLAG_CLASS(F, F_CLASS_OPTIONAL, 0, 0, F_FLAG) |
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FLAG_CLASS(FHARD, F_CLASS_OPTIONAL, 0, 0, F_FFAKE) |
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FLAG_CLASS(RL, F_CLASS_OPTIONAL, 0, 0, F_RL) |
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FLAG_CLASS(AQ, F_CLASS_OPTIONAL, 0, 0, F_AQ) |
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FLAG_CLASS(ATOP, F_CLASS_REQUIRED, 0, 0, F_ATO_ADD, F_ATO_OR, F_ATO_AND, F_ATO_XOR, F_ATO_MINU, F_ATO_MAXU, F_ATO_MIN, F_ATO_MAX) |
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FLAG_CLASS(T, F_CLASS_OPTIONAL, 0, 0, F_NT, F_T) |
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FLAG_CLASS(D, F_CLASS_OPTIONAL, 0, 0, F_ND, F_D) |
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FLAG_CLASS(DNZ_D, F_CLASS_OPTIONAL, 0, 0, F_DNZ_ND, F_DNZ_D) |
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FLAG_CLASS(DHARD, F_CLASS_OPTIONAL, 0, 0, F_DFAKE) |
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FLAG_CLASS(DI20, F_CLASS_OPTIONAL, 0, 0, F_DI11) |
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FLAG_CLASS(DI14, F_CLASS_OPTIONAL, 0, 0, F_DI14) |
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FLAG_CLASS(DI16, F_CLASS_OPTIONAL, 0, 0, F_DI15) |
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FLAG_CLASS(DI26, F_CLASS_OPTIONAL, 0, 0, F_DI5) |
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FLAG_CLASS(X25, F_CLASS_OPTIONAL, 0, 0, F_SIGN6) |
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FLAG_CLASS(X15, F_CLASS_OPTIONAL, 0, 0, F_SIGN16) |
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FLAG_CLASS(XHARD, F_CLASS_OPTIONAL, 0, 0, F_SIGNX) |
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FLAG_CLASS(X, F_CLASS_OPTIONAL, 0, 0, F_SIGNX) |
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FLAG_CLASS(ZZ13, F_CLASS_OPTIONAL, 0, 0, F_SIZEB17, F_SIZEW17, F_H17) |
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FLAG_CLASS(ZZ23, F_CLASS_OPTIONAL, 0, 0, F_SIZEB7, F_SIZEW7, F_H7) |
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FLAG_CLASS(ZZ29, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1, F_SIZEW1, F_H1) |
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FLAG_CLASS(ZZW6, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1) |
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FLAG_CLASS(ZZH1, F_CLASS_OPTIONAL, 0, 0, F_SIZEW1, F_H1) |
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FLAG_CLASS(AS, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE) |
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FLAG_CLASS(AAHARD13, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE) |
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FLAG_CLASS(NE, F_CLASS_REQUIRED, 0, 0, F_NE) |
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/* ARC NPS400 Support: See comment near head of file. */ |
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FLAG_CLASS(NPS_CL, F_CLASS_REQUIRED, 0, 0, F_NPS_CL) |
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FLAG_CLASS(NPS_NA, F_CLASS_OPTIONAL, 0, 0, F_NPS_NA) |
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FLAG_CLASS(NPS_SR, F_CLASS_OPTIONAL, 0, 0, F_NPS_SR) |
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FLAG_CLASS(NPS_M, F_CLASS_OPTIONAL, 0, 0, F_NPS_M) |
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FLAG_CLASS(NPS_F, F_CLASS_OPTIONAL, 0, 0, F_NPS_FLAG) |
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FLAG_CLASS(NPS_R, F_CLASS_OPTIONAL, 0, 0, F_NPS_R) |
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FLAG_CLASS(NPS_SCHD_RW, F_CLASS_REQUIRED, 0, 0, F_NPS_RW, F_NPS_RD) |
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FLAG_CLASS(NPS_SCHD_TRIG, F_CLASS_REQUIRED, 0, 0, F_NPS_WFT) |
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FLAG_CLASS(NPS_SCHD_IE, F_CLASS_OPTIONAL, 0, 0, F_NPS_IE1, F_NPS_IE2, F_NPS_IE12) |
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FLAG_CLASS(NPS_SYNC, F_CLASS_REQUIRED, 0, 0, F_NPS_SYNC_RD, F_NPS_SYNC_WR) |
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FLAG_CLASS(NPS_HWS_OFF, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_OFF) |
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FLAG_CLASS(NPS_HWS_RESTORE, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_RESTORE) |
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FLAG_CLASS(NPS_SX, F_CLASS_OPTIONAL, 0, 0, F_NPS_SX) |
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FLAG_CLASS(NPS_AR_AL, F_CLASS_REQUIRED, 0, 0, F_NPS_AR, F_NPS_AL) |
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FLAG_CLASS(NPS_S, F_CLASS_REQUIRED, 0, 0, F_NPS_S) |
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FLAG_CLASS(NPS_ZNCV, F_CLASS_REQUIRED, 0, 0, F_NPS_ZNCV_RD, F_NPS_ZNCV_WR) |
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FLAG_CLASS(NPS_P0, F_CLASS_REQUIRED, 0, 0, F_NPS_P0) |
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FLAG_CLASS(NPS_P1, F_CLASS_REQUIRED, 0, 0, F_NPS_P1) |
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FLAG_CLASS(NPS_P2, F_CLASS_REQUIRED, 0, 0, F_NPS_P2) |
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FLAG_CLASS(NPS_P3, F_CLASS_REQUIRED, 0, 0, F_NPS_P3) |
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FLAG_CLASS(NPS_LDBIT_DI, F_CLASS_REQUIRED, 0, 0, F_NPS_LDBIT_DI) |
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FLAG_CLASS(NPS_LDBIT_CL1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL1) |
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FLAG_CLASS(NPS_LDBIT_CL2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL2) |
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FLAG_CLASS(NPS_LDBIT_X_1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1) |
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FLAG_CLASS(NPS_LDBIT_X_2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2) |
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FLAG_CLASS(NPS_CORE, F_CLASS_REQUIRED, 0, 0, F_NPS_CORE) |
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FLAG_CLASS(NPS_CLSR, F_CLASS_REQUIRED, 0, 0, F_NPS_CLSR) |
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FLAG_CLASS(NPS_ALL, F_CLASS_REQUIRED, 0, 0, F_NPS_ALL) |
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FLAG_CLASS(NPS_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_GIC) |
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FLAG_CLASS(NPS_RSPI_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_RSPI_GIC) |
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FLAG_CLASS(FPCC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, insert_fs2, extract_fs2, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T) |
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FLAG_CLASS(AA_128, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_AA128, F_AA128W, F_AA128B, F_AA128S) |
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FLAG_CLASS(AS_128, F_CLASS_OPTIONAL, 0, 0, F_AA128S) |
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FLAG_CLASS(AA_128S, F_CLASS_OPTIONAL | F_CLASS_WB, insert_qq, extract_qq, F_AA128, F_AA128W, F_AA128B, F_AA128S) |
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FLAG_CLASS(AS_128S, F_CLASS_OPTIONAL, insert_qq, extract_qq, F_AA128S) |
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@ -1,179 +0,0 @@ |
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/* ARC flag defintions. |
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Copyright (C) 2023 Free Software Foundation, Inc. |
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|
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Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
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Refactored by Cupertino Miranda (cmiranda@synopsys.com) |
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|
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This file is part of libopcodes. |
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|
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This library is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3, or (at your option) |
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any later version. |
|||
|
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It is distributed in the hope that it will be useful, but WITHOUT |
|||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
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License for more details. |
|||
|
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You should have received a copy of the GNU General Public License |
|||
along with this program; if not, write to the Free Software Foundation, |
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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|
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FLAG(ALWAYS, "al", 0, 0, 0, 0) |
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FLAG(RA, "ra", 0, 0, 0, 0) |
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FLAG(EQUAL, "eq", 1, 5, 0, 1) |
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FLAG(ZERO, "z", 1, 5, 0, 0) |
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FLAG(NOTEQUAL, "ne", 2, 5, 0, 1) |
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FLAG(NOTZERO, "nz", 2, 5, 0, 0) |
|||
FLAG(POZITIVE, "p", 3, 5, 0, 1) |
|||
FLAG(PL, "pl", 3, 5, 0, 0) |
|||
FLAG(NEGATIVE, "n", 4, 5, 0, 1) |
|||
FLAG(MINUS, "mi", 4, 5, 0, 0) |
|||
FLAG(CARRY, "c", 5, 5, 0, 1) |
|||
FLAG(CARRYSET, "cs", 5, 5, 0, 0) |
|||
FLAG(LOWER, "lo", 5, 5, 0, 0) |
|||
FLAG(CARRYCLR, "cc", 6, 5, 0, 0) |
|||
FLAG(NOTCARRY, "nc", 6, 5, 0, 1) |
|||
FLAG(HIGHER, "hs", 6, 5, 0, 0) |
|||
FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0) |
|||
FLAG(OVERFLOW, "v", 7, 5, 0, 1) |
|||
FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1) |
|||
FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0) |
|||
FLAG(GT, "gt", 9, 5, 0, 1) |
|||
FLAG(GE, "ge", 10, 5, 0, 1) |
|||
FLAG(LT, "lt", 11, 5, 0, 1) |
|||
FLAG(LE, "le", 12, 5, 0, 1) |
|||
FLAG(HI, "hi", 13, 5, 0, 1) |
|||
FLAG(LS, "ls", 14, 5, 0, 1) |
|||
FLAG(PNZ, "pnz", 15, 5, 0, 1) |
|||
FLAG(NJ, "nj", 21, 5, 0, 1) |
|||
FLAG(NM, "nm", 23, 5, 0, 1) |
|||
FLAG(NO_T, "nt", 24, 5, 0, 1) |
|||
|
|||
/* FLAG. */ |
|||
FLAG(FLAG, "f", 1, 1, 15, 1) |
|||
FLAG(FFAKE, "f", 0, 0, 0, 1) |
|||
FLAG(AQ, "aq", 1, 1, 15, 1) |
|||
FLAG(RL, "rl", 1, 1, 15, 1) |
|||
|
|||
/* Atomic operations. */ |
|||
FLAG(ATO_ADD, "add", 0, 3, 0, 1) |
|||
FLAG(ATO_OR, "or", 1, 3, 0, 1) |
|||
FLAG(ATO_AND, "and", 2, 3, 0, 1) |
|||
FLAG(ATO_XOR, "xor", 3, 3, 0, 1) |
|||
FLAG(ATO_MINU, "minu", 4, 3, 0, 1) |
|||
FLAG(ATO_MAXU, "maxu", 5, 3, 0, 1) |
|||
FLAG(ATO_MIN, "min", 6, 3, 0, 1) |
|||
FLAG(ATO_MAX, "max", 7, 3, 0, 1) |
|||
|
|||
/* Delay slot. */ |
|||
FLAG(ND, "nd", 0, 1, 5, 0) |
|||
FLAG(D, "d", 1, 1, 5, 1) |
|||
FLAG(DFAKE, "d", 0, 0, 0, 1) |
|||
FLAG(DNZ_ND, "nd", 0, 1, 16, 0) |
|||
FLAG(DNZ_D, "d", 1, 1, 16, 1) |
|||
|
|||
/* Data size. */ |
|||
FLAG(SIZEB1, "b", 1, 2, 1, 1) |
|||
FLAG(SIZEB7, "b", 1, 2, 7, 1) |
|||
FLAG(SIZEB17, "b", 1, 2, 17, 1) |
|||
FLAG(SIZEW1, "w", 2, 2, 1, 0) |
|||
FLAG(SIZEW7, "w", 2, 2, 7, 0) |
|||
FLAG(SIZEW17, "w", 2, 2, 17, 0) |
|||
|
|||
/* Sign extension. */ |
|||
FLAG(SIGN6, "x", 1, 1, 6, 1) |
|||
FLAG(SIGN16, "x", 1, 1, 16, 1) |
|||
FLAG(SIGNX, "x", 0, 0, 0, 1) |
|||
|
|||
/* Address write-back modes. */ |
|||
FLAG(A3, "a", 1, 2, 3, 0) |
|||
FLAG(A9, "a", 1, 2, 9, 0) |
|||
FLAG(A22, "a", 1, 2, 22, 0) |
|||
FLAG(AW3, "aw", 1, 2, 3, 1) |
|||
FLAG(AW9, "aw", 1, 2, 9, 1) |
|||
FLAG(AW22, "aw", 1, 2, 22, 1) |
|||
FLAG(AB3, "ab", 2, 2, 3, 1) |
|||
FLAG(AB9, "ab", 2, 2, 9, 1) |
|||
FLAG(AB22, "ab", 2, 2, 22, 1) |
|||
FLAG(AS3, "as", 3, 2, 3, 1) |
|||
FLAG(AS9, "as", 3, 2, 9, 1) |
|||
FLAG(AS22, "as", 3, 2, 22, 1) |
|||
FLAG(ASFAKE, "as", 0, 0, 0, 1) |
|||
|
|||
/* address writebacks for 128-bit loads. |
|||
,---.---.----------. |
|||
| X | D | mnemonic | |
|||
|---+---+----------| |
|||
| 0 | 0 | none | |
|||
| 0 | 1 | as | |
|||
| 1 | 0 | a/aw | |
|||
| 1 | 1 | ab | |
|||
`---^---^----------' */ |
|||
FLAG(AA128, "a", 2, 2, 15, 0) |
|||
FLAG(AA128W, "aw", 2, 2, 15, 1) |
|||
FLAG(AA128B, "ab", 3, 2, 15, 1) |
|||
FLAG(AA128S, "as", 1, 2, 15, 1) |
|||
|
|||
/* Cache bypass. */ |
|||
FLAG(DI5, "di", 1, 1, 5, 1) |
|||
FLAG(DI11, "di", 1, 1, 11, 1) |
|||
FLAG(DI14, "di", 1, 1, 14, 1) |
|||
FLAG(DI15, "di", 1, 1, 15, 1) |
|||
|
|||
/* ARCv2 specific. */ |
|||
FLAG(NT, "nt", 0, 1, 3, 1) |
|||
FLAG(T, "t", 1, 1, 3, 1) |
|||
FLAG(H1, "h", 2, 2, 1, 1) |
|||
FLAG(H7, "h", 2, 2, 7, 1) |
|||
FLAG(H17, "h", 2, 2, 17, 1) |
|||
/* Fake */ |
|||
FLAG(SIZED, "dd", 8, 0, 0, 0) |
|||
/* Fake */ |
|||
FLAG(SIZEL, "dl", 8, 0, 0, 0) |
|||
/* Fake */ |
|||
FLAG(SIZEW, "xx", 4, 0, 0, 0) |
|||
|
|||
/* Fake Flags. */ |
|||
FLAG(NE, "ne", 0, 0, 0, 1) |
|||
|
|||
/* ARC NPS400 Support: See comment near head of arcxx-opc.inc file. */ |
|||
FLAG(NPS_CL, "cl", 0, 0, 0, 1) |
|||
FLAG(NPS_NA, "na", 1, 1, 9, 1) |
|||
FLAG(NPS_SR, "s", 1, 1, 13, 1) |
|||
FLAG(NPS_M, "m", 1, 1, 7, 1) |
|||
FLAG(NPS_FLAG, "f", 1, 1, 20, 1) |
|||
FLAG(NPS_R, "r", 1, 1, 15, 1) |
|||
FLAG(NPS_RW, "rw", 0, 1, 7, 1) |
|||
FLAG(NPS_RD, "rd", 1, 1, 7, 1) |
|||
FLAG(NPS_WFT, "wft", 0, 0, 0, 1) |
|||
FLAG(NPS_IE1, "ie1", 1, 2, 8, 1) |
|||
FLAG(NPS_IE2, "ie2", 2, 2, 8, 1) |
|||
FLAG(NPS_IE12, "ie12", 3, 2, 8, 1) |
|||
FLAG(NPS_SYNC_RD, "rd", 0, 1, 6, 1) |
|||
FLAG(NPS_SYNC_WR, "wr", 1, 1, 6, 1) |
|||
FLAG(NPS_HWS_OFF, "off", 0, 0, 0, 1) |
|||
FLAG(NPS_HWS_RESTORE, "restore", 0, 0, 0, 1) |
|||
FLAG(NPS_SX, "sx", 1, 1, 14, 1) |
|||
FLAG(NPS_AR, "ar", 0, 1, 0, 1) |
|||
FLAG(NPS_AL, "al", 1, 1, 0, 1) |
|||
FLAG(NPS_S, "s", 0, 0, 0, 1) |
|||
FLAG(NPS_ZNCV_RD, "rd", 0, 1, 15, 1) |
|||
FLAG(NPS_ZNCV_WR, "wr", 1, 1, 15, 1) |
|||
FLAG(NPS_P0, "p0", 0, 0, 0, 1) |
|||
FLAG(NPS_P1, "p1", 0, 0, 0, 1) |
|||
FLAG(NPS_P2, "p2", 0, 0, 0, 1) |
|||
FLAG(NPS_P3, "p3", 0, 0, 0, 1) |
|||
FLAG(NPS_LDBIT_DI, "di", 0, 0, 0, 1) |
|||
FLAG(NPS_LDBIT_CL1, "cl", 1, 1, 6, 1) |
|||
FLAG(NPS_LDBIT_CL2, "cl", 1, 1, 16, 1) |
|||
FLAG(NPS_LDBIT_X2_1, "x2", 1, 2, 9, 1) |
|||
FLAG(NPS_LDBIT_X2_2, "x2", 1, 2, 22, 1) |
|||
FLAG(NPS_LDBIT_X4_1, "x4", 2, 2, 9, 1) |
|||
FLAG(NPS_LDBIT_X4_2, "x4", 2, 2, 22, 1) |
|||
FLAG(NPS_CORE, "core", 1, 3, 6, 1) |
|||
FLAG(NPS_CLSR, "clsr", 2, 3, 6, 1) |
|||
FLAG(NPS_ALL, "all", 3, 3, 6, 1) |
|||
FLAG(NPS_GIC, "gic", 4, 3, 6, 1) |
|||
FLAG(NPS_RSPI_GIC, "gic", 5, 3, 6, 1) |
|||
File diff suppressed because it is too large
@ -1,502 +0,0 @@ |
|||
/* ARC operands defintions. |
|||
Copyright (C) 2023 Free Software Foundation, Inc. |
|||
|
|||
Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
|||
Refactored by Cupertino Miranda (cmiranda@synopsys.com) |
|||
|
|||
This file is part of libopcodes. |
|||
|
|||
This library is free software; you can redistribute it and/or modify |
|||
it under the terms of the GNU General Public License as published by |
|||
the Free Software Foundation; either version 3, or (at your option) |
|||
any later version. |
|||
|
|||
It is distributed in the hope that it will be useful, but WITHOUT |
|||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
|||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
|||
License for more details. |
|||
|
|||
You should have received a copy of the GNU General Public License |
|||
along with this program; if not, write to the Free Software Foundation, |
|||
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
|||
|
|||
|
|||
/* |
|||
* ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) |
|||
* |
|||
* BITS => The number of bits in the operand. |
|||
* SHIFT => How far the operand is left shifted in the instruction. |
|||
* RELO => The default relocation type for this operand. |
|||
* FLAGS => One bit syntax flags. |
|||
* FUN => Insertion function. This is used by the assembler. |
|||
*/ |
|||
|
|||
ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0) |
|||
|
|||
/* The plain integer register fields. Used by 32 bit instructions. */ |
|||
ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0, 0) |
|||
ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0) |
|||
ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb) |
|||
ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb) |
|||
ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, insert_rbb, extract_rbb) |
|||
ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0, 0) |
|||
ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0, 0) |
|||
ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb) |
|||
|
|||
ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0) |
|||
ARC_OPERAND(RAD_CHK, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0) |
|||
ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0) |
|||
ARC_OPERAND(RBD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb) |
|||
ARC_OPERAND(RBDdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb) |
|||
|
|||
/* The plain integer register fields. Used by short instructions. */ |
|||
ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras) |
|||
ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras) |
|||
ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs) |
|||
ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs) |
|||
ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs) |
|||
ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs) |
|||
ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs) |
|||
ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs) |
|||
|
|||
/* 6bit register field 'h' used by V1 cpus. */ |
|||
ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1) |
|||
/* 5bit register field 'h' used by V2 cpus. */ |
|||
ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2) |
|||
ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2) |
|||
ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2) |
|||
ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2) |
|||
|
|||
ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s) |
|||
ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s) |
|||
|
|||
/* Fix registers. */ |
|||
ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0) |
|||
ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0) |
|||
ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1) |
|||
ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1) |
|||
ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2) |
|||
ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2) |
|||
ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3) |
|||
ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3) |
|||
ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp) |
|||
ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp) |
|||
ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp) |
|||
ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp) |
|||
ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp) |
|||
ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp) |
|||
|
|||
ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl) |
|||
|
|||
ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink) |
|||
ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink) |
|||
|
|||
ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1) |
|||
ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2) |
|||
|
|||
/* Long immediate. */ |
|||
ARC_OPERAND(LIMM, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0) |
|||
ARC_OPERAND(LIMM_S, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0) |
|||
ARC_OPERAND(LO32, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM, insert_limm, 0) |
|||
ARC_OPERAND(HI32, 32, 0, BFD_RELOC_ARC_HI32_ME, ARC_OPERAND_LIMM, insert_limm, 0) |
|||
ARC_OPERAND(LIMM34, 34, 0, BFD_RELOC_ARC_PCLO32_ME_2, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_limm, 0) |
|||
ARC_OPERAND(XIMM_S, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0) |
|||
ARC_OPERAND(XIMM, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0) |
|||
ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0) |
|||
ARC_OPERAND(XIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE | ARC_OPERAND_SIGNED, insert_limm, 0) |
|||
|
|||
/* Special operands. */ |
|||
ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) |
|||
ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) |
|||
ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) |
|||
ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) |
|||
ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) |
|||
|
|||
ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, insert_rrange, extract_rrange) |
|||
ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_r13el, extract_rrange) |
|||
ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_fpel, extract_fpel) |
|||
ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_blinkel, extract_blinkel) |
|||
ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_pclel, extract_pclel) |
|||
|
|||
/* Fake operand to handle the T flag. */ |
|||
ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0) |
|||
ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0) |
|||
|
|||
/* Fake operand to handle the T flag. */ |
|||
ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0) |
|||
/* Fake operand to handle the T flag. */ |
|||
ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0) |
|||
|
|||
/* UIMM6_20 mask = 00000000000000000000111111000000. */ |
|||
ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20) |
|||
|
|||
/* Exactly like the above but used by relaxation. */ |
|||
ARC_OPERAND(UIMM6_20R, 6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm6_20, extract_uimm6_20) |
|||
|
|||
/* SIMM12_20 mask = 00000000000000000000111111222222. */ |
|||
ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20) |
|||
|
|||
/* Exactly like the above but used by relaxation. */ |
|||
ARC_OPERAND(SIMM12_20R, 12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, insert_simm12_20, extract_simm12_20) |
|||
|
|||
/* UIMM12_20 mask = 00000000000000000000111111222222. */ |
|||
ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20) |
|||
|
|||
/* SIMM3_5_S mask = 0000011100000000. */ |
|||
ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, insert_simm3s, extract_simm3s) |
|||
|
|||
/* UIMM7_A32_11_S mask = 0000000000011111. */ |
|||
ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s) |
|||
|
|||
/* The same as above but used by relaxation. */ |
|||
ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s) |
|||
|
|||
ARC_OPERAND(UIMM9_A32_11_S, 9, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm9_a32_11_s, extract_uimm9_a32_11_s) |
|||
|
|||
/* UIMM7_9_S mask = 0000000001111111. */ |
|||
ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s) |
|||
|
|||
/* UIMM3_13_S mask = 0000000000000111. */ |
|||
ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s) |
|||
|
|||
/* Exactly like the above but used for relaxation. */ |
|||
ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm3_13_s, extract_uimm3_13_s) |
|||
|
|||
/* SIMM11_A32_7_S mask = 0000000111111111. */ |
|||
ARC_OPERAND(SIMM11_A32_7_S, 11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s) |
|||
|
|||
/* UIMM6_13_S mask = 0000000002220111. */ |
|||
ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s) |
|||
/* UIMM5_11_S mask = 0000000000011111. */ |
|||
ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, extract_uimm5_11_s) |
|||
|
|||
/* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ |
|||
ARC_OPERAND(SIMM9_A16_8, 9, 0, BFD_RELOC_ARC_S9H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, extract_simm9_a16_8) |
|||
|
|||
/* UIMM6_8 mask = 00000000000000000000111111000000. */ |
|||
ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8) |
|||
|
|||
/* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ |
|||
ARC_OPERAND(SIMM21_A16_5, 21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a16_5, extract_simm21_a16_5) |
|||
|
|||
/* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ |
|||
ARC_OPERAND(SIMM25_A16_5, 25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a16_5, extract_simm25_a16_5) |
|||
|
|||
/* SIMM10_A16_7_S mask = 0000000111111111. */ |
|||
ARC_OPERAND(SIMM10_A16_7_S, 10, 0, BFD_RELOC_ARC_S10H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, extract_simm10_a16_7_s) |
|||
|
|||
ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s) |
|||
|
|||
/* SIMM7_A16_10_S mask = 0000000000111111. */ |
|||
ARC_OPERAND(SIMM7_A16_10_S, 7, 0, BFD_RELOC_ARC_S7H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, extract_simm7_a16_10_s) |
|||
|
|||
/* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ |
|||
ARC_OPERAND(SIMM21_A32_5, 21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, extract_simm21_a32_5) |
|||
|
|||
/* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ |
|||
ARC_OPERAND(SIMM25_A32_5, 25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, extract_simm25_a32_5) |
|||
|
|||
/* SIMM13_A32_5_S mask = 0000011111111111. */ |
|||
ARC_OPERAND(SIMM13_A32_5_S, 13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, extract_simm13_a32_5_s) |
|||
|
|||
/* SIMM8_A16_9_S mask = 0000000001111111. */ |
|||
ARC_OPERAND(SIMM8_A16_9_S, 8, 0, BFD_RELOC_ARC_S8H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, extract_simm8_a16_9_s) |
|||
|
|||
/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */ |
|||
ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, extract_uimm10_6_s) |
|||
|
|||
/* UIMM3_23 mask = 00000000000000000000000111000000. */ |
|||
ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23) |
|||
|
|||
/* UIMM10_6_S mask = 0000001111111111. */ |
|||
ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s) |
|||
|
|||
ARC_OPERAND(UIMM10_13_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_13_s, extract_uimm10_13_s) |
|||
|
|||
/* UIMM6_11_S mask = 0000002200011110. */ |
|||
ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s) |
|||
|
|||
/* SIMM9_8 mask = 00000000111111112000000000000000. */ |
|||
ARC_OPERAND(SIMM9_8, 9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, insert_simm9_8, extract_simm9_8) |
|||
|
|||
/* The same as above but used by relaxation. */ |
|||
ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8) |
|||
|
|||
/* UIMM10_A32_8_S mask = 0000000011111111. */ |
|||
ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, extract_uimm10_a32_8_s) |
|||
|
|||
/* SIMM9_7_S mask = 0000000111111111. */ |
|||
ARC_OPERAND(SIMM9_7_S, 9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, extract_simm9_7_s) |
|||
|
|||
/* UIMM6_A16_11_S mask = 0000000000011111. */ |
|||
ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, extract_uimm6_a16_11_s) |
|||
|
|||
/* UIMM5_A32_11_S mask = 0000020000011000. */ |
|||
ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, extract_uimm5_a32_11_s) |
|||
|
|||
/* SIMM11_A32_13_S mask = 0000022222200111. */ |
|||
ARC_OPERAND(SIMM11_A32_13_S, 11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s) |
|||
|
|||
/* UIMM7_13_S mask = 0000000022220111. */ |
|||
ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s) |
|||
|
|||
/* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ |
|||
ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21) |
|||
|
|||
/* UIMM7_11_S mask = 0000022200011110. */ |
|||
ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s) |
|||
|
|||
/* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ |
|||
ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, extract_uimm7_a16_20) |
|||
|
|||
/* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ |
|||
ARC_OPERAND(SIMM13_A16_20, 13, 0, BFD_RELOC_ARC_S13H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, extract_simm13_a16_20) |
|||
|
|||
/* UIMM8_8_S mask = 0000000011111111. */ |
|||
ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s) |
|||
|
|||
/* The same as above but used for relaxation. */ |
|||
ARC_OPERAND(UIMM8_8R_S, 8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm8_8_s, extract_uimm8_8_s) |
|||
|
|||
/* W6 mask = 00000000000000000000111111000000. */ |
|||
ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6) |
|||
|
|||
/* UIMM6_5_S mask = 0000011111100000. */ |
|||
ARC_OPERAND(UIMM6_5_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s) |
|||
|
|||
/* ARC NPS400 Support: See comment near head of file. */ |
|||
ARC_OPERAND(NPS_R_DST_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC2_3B, 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2) |
|||
|
|||
ARC_OPERAND(NPS_R_DST, 6, 21, 0, ARC_OPERAND_IR, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC1, 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS, 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SRC_POS, 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SIZE, 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS_SZ, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SIZE_2B, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_UIMM8, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8) |
|||
|
|||
ARC_OPERAND(NPS_UIMM16, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_SIMM16, 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_RFLT_UIMM6, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6) |
|||
|
|||
ARC_OPERAND(NPS_XLDST_UIMM16, 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16) |
|||
|
|||
ARC_OPERAND(NPS_SRC2_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos) |
|||
|
|||
ARC_OPERAND(NPS_SRC1_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos) |
|||
|
|||
ARC_OPERAND(NPS_ADDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size) |
|||
|
|||
ARC_OPERAND(NPS_ANDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size) |
|||
|
|||
ARC_OPERAND(NPS_FXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size) |
|||
|
|||
ARC_OPERAND(NPS_WXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size) |
|||
|
|||
ARC_OPERAND(NPS_R_XLDST, 6, 5, 0, ARC_OPERAND_IR, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_DIV_UIMM4, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_QCMP_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size) |
|||
|
|||
ARC_OPERAND(NPS_QCMP_M1, 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1) |
|||
|
|||
ARC_OPERAND(NPS_QCMP_M2, 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2) |
|||
|
|||
ARC_OPERAND(NPS_QCMP_M3, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3) |
|||
|
|||
ARC_OPERAND(NPS_CALC_ENTRY_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size) |
|||
|
|||
ARC_OPERAND(NPS_R_DST_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC1_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC2_3B_SHORT, 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SIZE2, 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SIZE1, 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS3_POS4, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS4, 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS3, 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS2, 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_DST_POS1, 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SRC_POS4, 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SRC_POS3, 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SRC_POS2, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_SRC_POS1, 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_MOD4, 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_MOD3, 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_MOD2, 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_MOD1, 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BITOP_INS_EXT, 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext) |
|||
|
|||
ARC_OPERAND(NPS_FIELD_START_POS, 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_FIELD_SIZE, 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size) |
|||
|
|||
ARC_OPERAND(NPS_SHIFT_FACTOR, 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor) |
|||
|
|||
ARC_OPERAND(NPS_BITS_TO_SCRAMBLE, 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble) |
|||
|
|||
ARC_OPERAND(NPS_SRC2_POS_5B, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BDLEN_MAX_LEN, 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len) |
|||
|
|||
ARC_OPERAND(NPS_MIN_HOFS, 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs) |
|||
|
|||
ARC_OPERAND(NPS_PSBC, 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_DPI_DST, 5, 11, 0, ARC_OPERAND_IR, NULL, NULL) |
|||
|
|||
/* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B |
|||
but doesn't duplicate an operand. */ |
|||
ARC_OPERAND(NPS_DPI_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst) |
|||
|
|||
ARC_OPERAND(NPS_HASH_WIDTH, 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width) |
|||
|
|||
ARC_OPERAND(NPS_HASH_PERM, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_HASH_NONLINEAR, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_HASH_BASEMAT, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_HASH_LEN, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len) |
|||
|
|||
ARC_OPERAND(NPS_HASH_OFS, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_HASH_BASEMAT2, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_E4BY_INDEX0, 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_E4BY_INDEX1, 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_E4BY_INDEX2, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_E4BY_INDEX3, 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3) |
|||
|
|||
ARC_OPERAND(COLON, 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd) |
|||
|
|||
ARC_OPERAND(NPS_JID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid) |
|||
|
|||
ARC_OPERAND(NPS_LBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd) |
|||
|
|||
ARC_OPERAND(NPS_MBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd) |
|||
|
|||
ARC_OPERAND(NPS_SD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd) |
|||
|
|||
ARC_OPERAND(NPS_SM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm) |
|||
|
|||
ARC_OPERAND(NPS_XA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa) |
|||
|
|||
ARC_OPERAND(NPS_XD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd) |
|||
|
|||
ARC_OPERAND(NPS_CD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd) |
|||
|
|||
ARC_OPERAND(NPS_CBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd) |
|||
|
|||
ARC_OPERAND(NPS_CJID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid) |
|||
|
|||
ARC_OPERAND(NPS_CLBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd) |
|||
|
|||
ARC_OPERAND(NPS_CM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm) |
|||
|
|||
ARC_OPERAND(NPS_CSD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd) |
|||
|
|||
ARC_OPERAND(NPS_CXA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa) |
|||
|
|||
ARC_OPERAND(NPS_CXD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd) |
|||
|
|||
ARC_OPERAND(NPS_BD_TYPE, 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_BMU_NUM, 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff) |
|||
|
|||
ARC_OPERAND(NPS_PMU_NXT_DST, 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_WHASH_SIZE, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_size_16bit, extract_nps_size_16bit) |
|||
|
|||
ARC_OPERAND(NPS_PMU_NUM_JOB, 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job) |
|||
|
|||
ARC_OPERAND(NPS_DMA_IMM_ENTRY, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_entry, extract_nps_imm_entry) |
|||
|
|||
ARC_OPERAND(NPS_DMA_IMM_OFFSET, 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset) |
|||
|
|||
ARC_OPERAND(NPS_MISC_IMM_SIZE, 7, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_MISC_IMM_OFFSET, 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_misc_imm_offset, extract_nps_misc_imm_offset) |
|||
|
|||
ARC_OPERAND(NPS_R_DST_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC1_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC2_3B_48, 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2) |
|||
|
|||
ARC_OPERAND(NPS_R_DST_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC1_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst) |
|||
|
|||
ARC_OPERAND(NPS_R_SRC2_3B_64, 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2) |
|||
|
|||
ARC_OPERAND(NPS_RA_64, 6, 53, 0, ARC_OPERAND_IR, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_RB_64, 5, 48, 0, ARC_OPERAND_IR, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_RBdup_64, 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_RBdouble_64, 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64) |
|||
|
|||
ARC_OPERAND(NPS_RC_64, 5, 43, 0, ARC_OPERAND_IR, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_UIMM16_0_64, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) |
|||
|
|||
ARC_OPERAND(NPS_PROTO_SIZE, 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size) |
|||
|
|||
/* ARC64's floating point registers. */ |
|||
ARC_OPERAND(FA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0) |
|||
ARC_OPERAND(FB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0) |
|||
ARC_OPERAND(FC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, insert_fs2, extract_fs2) |
|||
ARC_OPERAND(FD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0) |
|||
|
|||
/* Double 128 registers, the same like above but only the odd ones |
|||
allowed. */ |
|||
ARC_OPERAND(FDA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0) |
|||
ARC_OPERAND(FDB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0) |
|||
ARC_OPERAND(FDC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, insert_fs2, extract_fs2) |
|||
ARC_OPERAND(FDD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0) |
|||
|
|||
/* 5bit integer registers used by fp instructions. */ |
|||
ARC_OPERAND(FRD, 5, 6, 0, ARC_OPERAND_IR, 0, 0) |
|||
ARC_OPERAND(FRB, 5, 0, 0, ARC_OPERAND_IR, insert_fs2, extract_fs2) |
|||
|
|||
/* 5bit unsigned immediate used by vfext and vfins. */ |
|||
ARC_OPERAND(UIMM5_FP, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_fs2, extract_fs2) |
|||
@ -1,834 +0,0 @@ |
|||
/* Opcode table for ARC64.
|
|||
Copyright (C) 2023 Free Software Foundation, Inc. |
|||
|
|||
Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
|||
|
|||
This file is part of libopcodes. |
|||
|
|||
This library is free software; you can redistribute it and/or modify |
|||
it under the terms of the GNU General Public License as published by |
|||
the Free Software Foundation; either version 3, or (at your option) |
|||
any later version. |
|||
|
|||
It is distributed in the hope that it will be useful, but WITHOUT |
|||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
|||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
|||
License for more details. |
|||
|
|||
You should have received a copy of the GNU General Public License |
|||
along with this program; if not, write to the Free Software Foundation, |
|||
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
|||
|
|||
#include "arcxx-opc.inc" |
|||
|
|||
#define F32_BR0 0x00 |
|||
#define F32_BR1 0x01 |
|||
#define F32_LD_OFFSET 0x02 |
|||
#define F32_ST_OFFSET 0x03 |
|||
#define F32_GEN4 0x04 |
|||
#define F32_EXT5 0x05 |
|||
#define F32_EXT6 0x06 |
|||
#define F32_APEX 0x07 |
|||
|
|||
#define F16_COMPACT0 0x08 |
|||
#define F16_COMPACT1 0x08 |
|||
#define F16_MOVL 0x08 |
|||
|
|||
#define F16_LD_ADD_SUB 0x09 |
|||
|
|||
#define LD_ST_R01 0x0A |
|||
#define LDI_S 0x0A |
|||
#define JLI_S_U10 0x0A |
|||
|
|||
#define F16_JLI_EI 0x0B |
|||
#define F32_GEN_OP64 0x0B |
|||
|
|||
/* Macros required for ARCv3 floating point instructions. */ |
|||
/* Flags. */ |
|||
#define FL_NONE { 0 } |
|||
#define FL_CC { C_FPCC } |
|||
|
|||
/* Arguments. */ |
|||
#define ARG_NONE { 0 } |
|||
#define ARG_64FP_3OP { FA, FB, FC, FD } |
|||
#define ARG_128FP_3OP { FDA, FDB, FDC, FDD } |
|||
#define ARG_64FP_2OP { FA, FB, FC } |
|||
#define ARG_64FP_CMP { FB, FC } |
|||
#define ARG_128FP_2OP { FDA, FDB, FDC } |
|||
#define ARG_64FP_1OP { FA, FC } |
|||
#define ARG_64FP_SOP { FA, FB } |
|||
#define ARG_128FP_SOP { FDA, FDB } |
|||
|
|||
#define ARG_64FP_CVI2F { FA, FRB } |
|||
#define ARG_64FP_CVF2I { FRD, FC } |
|||
|
|||
/* Macros to help generating floating point pattern instructions. */ |
|||
/* Define FP_TOP. */ |
|||
#define FIELDS1(word) (word & 0x1F) |
|||
#define FIELDS2(word) (((word & 0x07) << 24) | (((word >> 3) & 0x03) << 12)) |
|||
#define FIELDS3(word) ((word & 0x1F) << 19) |
|||
#define FIELDD(word) ((word & 0x1F) << 6) |
|||
#define FIELDTOP(word) (((word & 0x01) << 5) | ((word >> 1) & 0x07) << 16) |
|||
#define FIELDP(word) ((word & 0x03) << 14) |
|||
#define MASK_32BIT(VAL) (0xffffffff & (VAL)) |
|||
|
|||
#define INSNFP3OP(TOPF, P) \ |
|||
((0x1C << 27) | FIELDTOP (TOPF) | FIELDP (P) | (1 << 11)) |
|||
#define MINSNFP3OP \ |
|||
(MASK_32BIT (~(FIELDS1 (31) | FIELDS2 (31) | FIELDS3 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_DOP. */ |
|||
#define FIELDDOP(ops) ((ops & 0x1f) << 16) |
|||
|
|||
#define INSNFP2OP(DOPF, P) \ |
|||
((0x1C << 27) | FIELDDOP (DOPF) | FIELDP (P) | (1 << 5)) |
|||
#define MINSNFP2OP \ |
|||
(MASK_32BIT (~(FIELDS2 (31) | FIELDS1 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_CVF2F. */ |
|||
#define FIELDCVTF(WORD) ((WORD & 0x03) << 16) |
|||
#define FIELDU0(BIT) (BIT & 0x01) |
|||
#define FIELDU1(BIT) (BIT & 0x02) |
|||
#define FIELDU3(BIT) (BIT & 0x08) |
|||
#define FIELDU4(BIT) (BIT & 0x10) |
|||
|
|||
#define FP_CVF2F_MACHINE(CVTF, BIT) \ |
|||
((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \ |
|||
| (1 << 5) | (1 << 2) | FIELDU0 (BIT) | FIELDU3 (BIT) | FIELDU4 (BIT)) |
|||
#define MFP_CVF2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_RND. */ |
|||
#define FP_RND_MACHINE(CVTF, BIT) \ |
|||
((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) | (1 << 5) | (0x03 << 1) \ |
|||
| FIELDU3 (BIT)) |
|||
#define MFP_RND (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_CVF2I. */ |
|||
#define FP_CVF2I_MACHINE(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) \ |
|||
| FIELDCVTF (CVTF) | (1 << 5) | 1 \ |
|||
| FIELDU3 (BIT) | FIELDU1 (BIT)) |
|||
#define MFP_CVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FMVVF2I. */ |
|||
#define FM_VVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \ |
|||
| (1 << 5) | 1 << 4 | 1) |
|||
#define MFM_VVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_SOP. */ |
|||
#define FP_SOP_MACHINE(SOPF, P) \ |
|||
((0x1C << 27) | (0x02 << 21) | FIELDCVTF (SOPF) | FIELDP (P) | (1 << 5)) |
|||
#define MFP_SOP_MACHINE (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_COP. */ |
|||
#define FP_COP_MACHINE(COPF, P) \ |
|||
((0x1C << 27) | (0x09 << 19) | FIELDCVTF (COPF) | FIELDP (P) | (1 << 5)) |
|||
#define MFP_COP_MACHINE \ |
|||
(MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31)))) |
|||
|
|||
/* Define FP_ZOP. */ |
|||
#define INSNFPZOP(COPF) \ |
|||
((0x1C << 27) | (0x07 << 20) | FIELDCVTF (COPF) | (1 << 5)) |
|||
|
|||
/* Define FP_VMVI. */ |
|||
#define INSNFPVMVI(WMVF, P) \ |
|||
((0x1C << 27) | (0x05 << 20) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5)) |
|||
#define MINSNFPCOP (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31)))) |
|||
#define MINSNFPVMVIZ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_VMVR. */ |
|||
#define INSNFPVMVR(WMVF, P) \ |
|||
((0x1C << 27) | (0x01 << 23) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5)) |
|||
#define MINSNFPVMVR (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31)))) |
|||
|
|||
/* Define FP_CVI2F. */ |
|||
#define INSNFPCVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \ |
|||
| (1 << 5) | FIELDU3 (BIT) | FIELDU1 (BIT)) |
|||
#define MINSNFPCVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FMVI2F. */ |
|||
#define INSNFMVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \ |
|||
| (1 << 5) | (1 << 4)) |
|||
#define MINSNFMVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FMVF2I. */ |
|||
#define INSNFMVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \ |
|||
| (1 << 5) | (1 << 4) | (1)) |
|||
#define MINSNFMVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) |
|||
|
|||
/* Define FP_LOAD. */ |
|||
#define FP_LOAD_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \ |
|||
| ((D & 0x01) << 5)) |
|||
#define MSK_FP_LOAD (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \ |
|||
| (0x1FF << 15)))) |
|||
|
|||
#define FP_LSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \ |
|||
| FIELDB(62) | ((D & 0x01) << 5)) |
|||
#define MSK_FP_SYM (MASK_32BIT (~(FIELDD (31)))) |
|||
|
|||
/* Define FP_STORE. */ |
|||
#define FP_STORE_ENCODING(SIZE, D) ((0x0D << 27) | ((SIZE & 0x03) << 1) \ |
|||
| ((D & 0x01) << 5) | (1)) |
|||
#define MSK_FP_STORE (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \ |
|||
| (0x1FF << 15)))) |
|||
#define FP_SSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \ |
|||
| FIELDB(62) | ((D & 0x01) << 5) | (1)) |
|||
|
|||
/* FP Load/Store. */ |
|||
#define FP_LOAD(NAME, SIZE, D) \ |
|||
{ #NAME, FP_LOAD_ENCODING (SIZE, D), MSK_FP_LOAD, ARC_OPCODE_ARC64, LOAD, \ |
|||
NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \ |
|||
{ #NAME, FP_LSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \ |
|||
NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE }, |
|||
|
|||
#define FP_STORE(NAME, SIZE, D) \ |
|||
{ #NAME, FP_STORE_ENCODING (SIZE, D), MSK_FP_STORE, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \ |
|||
{ #NAME, FP_SSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \ |
|||
NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE }, |
|||
|
|||
/* Macros used to generate conversion instructions. */ |
|||
#define FMVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ |
|||
{ NAME, INSNFMVF2I (OPS, BIT), MINSNFMVF2I, CPU, CLASS, \ |
|||
SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FMVF2I(NAME, OPS, BIT) \ |
|||
FMVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ |
|||
BIT, ARG_64FP_CVF2I) |
|||
|
|||
#define FMVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ |
|||
{ NAME, INSNFMVI2F (OPS, BIT), MINSNFMVI2F, CPU, CLASS, \ |
|||
SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FMVI2F(NAME, OPS, BIT) \ |
|||
FMVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ |
|||
BIT, ARG_64FP_CVI2F) |
|||
|
|||
#define FP_RND_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ |
|||
{ NAME, FP_RND_MACHINE (OPS, BIT), MFP_RND, CPU, CLASS, \ |
|||
SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FP_RND(NAME, OPS, BIT) \ |
|||
FP_RND_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ |
|||
BIT, ARG_64FP_1OP) |
|||
|
|||
#define FP_CVF2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ |
|||
{ NAME, FP_CVF2F_MACHINE (OPS, BIT), MFP_CVF2F, CPU, CLASS, \ |
|||
SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FP_CVF2F(NAME, OPS, BIT) \ |
|||
FP_CVF2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ |
|||
BIT, ARG_64FP_1OP) |
|||
|
|||
#define FP_CVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ |
|||
{ NAME, FP_CVF2I_MACHINE (OPS, BIT), MFP_CVF2I, CPU, CLASS, \ |
|||
SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FP_CVF2I(NAME, OPS, BIT) \ |
|||
FP_CVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ |
|||
BIT, ARG_64FP_CVF2I) |
|||
|
|||
#define FP_CVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ |
|||
{ NAME, INSNFPCVI2F (OPS, BIT), MINSNFPCVI2F, CPU, CLASS, \ |
|||
SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FP_CVI2F(NAME, OPS, BIT) \ |
|||
FP_CVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ |
|||
BIT, ARG_64FP_CVI2F) |
|||
|
|||
/* Macro to generate 1 operand extension instruction. */ |
|||
#define FP_SOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ |
|||
{ NAME, FP_SOP_MACHINE (OPS, PRC), MFP_SOP_MACHINE, CPU, CLASS, SCLASS, \ |
|||
ARG, FL_NONE }, |
|||
|
|||
#define FP_SOP(NAME, OPS, PRECISION) \ |
|||
FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_64FP_SOP) |
|||
|
|||
#define FP_SOP_D(NAME, OPS, PRECISION) \ |
|||
FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_128FP_SOP) |
|||
|
|||
/* Macro to generate 2 operand extension instruction. */ |
|||
#define FP_DOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ |
|||
{ NAME, INSNFP2OP (OPS, PRC), MINSNFP2OP, CPU, CLASS, SCLASS, \ |
|||
ARG, FL_NONE }, |
|||
|
|||
#define FP_DOP(NAME, OPS, PRECISION) \ |
|||
FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_64FP_2OP) |
|||
|
|||
#define FP_DOPC_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ |
|||
{ NAME, INSNFP2OP (OPS, PRC) | FIELDD (0), MINSNFP2OP, CPU, \ |
|||
CLASS, SCLASS, ARG, FL_NONE }, |
|||
|
|||
#define FP_DOP_C(NAME, OPS, PRECISION) \ |
|||
FP_DOPC_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_64FP_CMP) |
|||
|
|||
#define FP_DOP_D(NAME, OPS, PRECISION) \ |
|||
FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_128FP_2OP) |
|||
|
|||
/* Macro to generate 3 operand generic instruction. */ |
|||
#define FP_TOP_INSN(NAME, CPU, CLASS, SCLASS, TOPF, P, ARG) \ |
|||
{ NAME, INSNFP3OP (TOPF, P), MINSNFP3OP, CPU, CLASS, SCLASS, \ |
|||
ARG, FL_NONE }, |
|||
|
|||
#define FP_TOP(NAME, OPS, PRECISION) \ |
|||
FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_64FP_3OP) |
|||
|
|||
#define FP_TOP_D(NAME, OPS, PRECISION) \ |
|||
FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_128FP_3OP) |
|||
|
|||
/* Conditional mov instructions. */ |
|||
#define FP_COP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ |
|||
{ NAME, FP_COP_MACHINE (OPS, PRC), MFP_COP_MACHINE, CPU, CLASS, SCLASS, \ |
|||
ARG, FL_CC }, |
|||
|
|||
#define FP_COP(NAME, OPS, PRECISION) \ |
|||
FP_COP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, COPF_ ## OPS, \ |
|||
P_ ## PRECISION, ARG_64FP_SOP) |
|||
|
|||
#define FP_EXT(NAME, PRECISION) \ |
|||
{#NAME, INSNFPVMVI (0x00, P_ ## PRECISION), MINSNFPCOP, \ |
|||
ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, \ |
|||
BRAKETdup }, FL_NONE }, \ |
|||
{#NAME, INSNFPVMVR (0x00, P_ ## PRECISION), MINSNFPVMVR, \ |
|||
ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup}, \ |
|||
FL_NONE }, |
|||
|
|||
#define FP_INS(NAME, PRECISION) \ |
|||
{#NAME, INSNFPVMVI (0x01, P_ ## PRECISION), MINSNFPCOP, \ |
|||
ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, \ |
|||
FB }, FL_NONE }, \ |
|||
{#NAME, INSNFPVMVR (0x01, P_ ## PRECISION), MINSNFPVMVR, \ |
|||
ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, \ |
|||
FB }, FL_NONE }, |
|||
|
|||
#define FP_REP(NAME, PRECISION) \ |
|||
{#NAME, INSNFPVMVI (0x02, P_ ## PRECISION) | FIELDS2 (0x00), \ |
|||
MINSNFPVMVIZ, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, FL_NONE }, |
|||
|
|||
|
|||
/* Common combinations of FLAGS. */ |
|||
#define FLAGS_NONE { 0 } |
|||
#define FLAGS_F { C_F } |
|||
#define FLAGS_CC { C_CC } |
|||
#define FLAGS_CCF { C_CC, C_F } |
|||
|
|||
/* Common combination of arguments. */ |
|||
#define ARG_NONE { 0 } |
|||
#define ARG_32BIT_RARBRC { RA, RB, RC } |
|||
#define ARG_32BIT_ZARBRC { ZA, RB, RC } |
|||
#define ARG_32BIT_RBRBRC { RB, RBdup, RC } |
|||
#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } |
|||
#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } |
|||
#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } |
|||
#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } |
|||
#define ARG_32BIT_RALIMMRC { RA, LIMM, RC } |
|||
#define ARG_32BIT_RARBLIMM { RA, RB, LIMM } |
|||
#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC } |
|||
#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } |
|||
|
|||
#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } |
|||
#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 } |
|||
#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 } |
|||
|
|||
#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 } |
|||
#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup } |
|||
#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup } |
|||
|
|||
#define ARG_32BIT_RBRC { RB, RC } |
|||
#define ARG_32BIT_ZARC { ZA, RC } |
|||
#define ARG_32BIT_RBU6 { RB, UIMM6_20 } |
|||
#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 } |
|||
#define ARG_32BIT_RBLIMM { RB, LIMM } |
|||
#define ARG_32BIT_ZALIMM { ZA, LIMM } |
|||
|
|||
#define ARG_32BIT_RAXIMMRC { RA, XIMM, RC } |
|||
#define ARG_32BIT_RARBXIMM { RA, RB, XIMM } |
|||
#define ARG_32BIT_RBRBXIMM { RB, RBdup, XIMM } |
|||
#define ARG_32BIT_RAXIMMU6 { RA, XIMM, UIMM6_20 } |
|||
|
|||
/* Macro to generate 2 operand extension instruction. */ |
|||
#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ |
|||
{ NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRC, FL }, \ |
|||
{ NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZARC, FL }, \ |
|||
{ NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBU6, FL }, \ |
|||
{ NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZAU6, FL }, \ |
|||
{ NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBLIMM, FL }, \ |
|||
{ NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMM, FL }, |
|||
|
|||
#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ |
|||
EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F) |
|||
|
|||
/* Macro to generate 3 operand extesion instruction. */ |
|||
#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ |
|||
{ NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZARBRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBRC, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZARBU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBU6, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBS12, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RALIMMRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBLIMM, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZARBLIMM, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RALIMMU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMS12, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RALIMMLIMM, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZALIMMLIMM, FLAGS_CCF }, |
|||
|
|||
|
|||
/* Generate sign extend 32-bit immediate instructions. */ |
|||
#define INSN3OP_AXC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (60)) |
|||
#define INSN3OP_ABX(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (60)) |
|||
#define INSN3OP_CBBX(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (60)) |
|||
#define INSN3OP_AXU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (60)) |
|||
|
|||
/* Macro to generate 3 operand 64bit instruction. */ |
|||
#define OP64INSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ |
|||
{ NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZARBRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBRC, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_ZARBU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBU6, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBS12, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_AXC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RAXIMMRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_ABX (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBXIMM, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_CBBX (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBXIMM, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_AXU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RAXIMMU6, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RALIMMRC, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RARBLIMM, FLAGS_F }, \ |
|||
{ NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ |
|||
{ NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ |
|||
ARG_32BIT_RALIMMU6, FLAGS_F }, |
|||
|
|||
|
|||
#define STDL_ENCODING(K, ZZ) ((F32_ST_OFFSET << 27) | (1 << 5) | (ZZ << 1) \ |
|||
| (K)) |
|||
#define MSK_STDL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \ |
|||
| (0x3 << 3)))) |
|||
#define STDL_ASYM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDB (X) \ |
|||
| (1 << 5) | (ZZ << 1) | (K)) |
|||
#define STDL_DIMM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDC (X) \ |
|||
| (1 << 5) | (ZZ << 1) | (K)) |
|||
|
|||
/* stdl<.aa> c,[b,s9]
|
|||
stdl<.aa> w6,[b,s9] |
|||
stdl<.as> c,[ximm] |
|||
stdl<.as> w6,[ximm] |
|||
stdl<.aa> ximm,[b,s9] |
|||
stdl<.aa> limm,[b,s9] |
|||
*/ |
|||
#define STDL \ |
|||
{ "stdl", STDL_ENCODING (0, 0x03), MSK_STDL, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ |
|||
{ "stdl", STDL_ENCODING (1, 0x02), MSK_STDL, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ |
|||
{ "stdl", STDL_ASYM_ENCODING (0, 0x03, 60), 0xFF007027, ARC_OPCODE_ARC64, \ |
|||
STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, {C_AS27 }}, \ |
|||
{ "stdl", STDL_ASYM_ENCODING (1, 0x02, 60), 0xFF007027, ARC_OPCODE_ARC64, \ |
|||
STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \ |
|||
{ "stdl", STDL_ASYM_ENCODING (0, 0x03, 62), 0xFF007027, ARC_OPCODE_ARC64, \ |
|||
STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, {C_AS27 }}, \ |
|||
{ "stdl", STDL_ASYM_ENCODING (1, 0x02, 62), 0xFF007027, ARC_OPCODE_ARC64, \ |
|||
STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \ |
|||
{ "stdl", STDL_DIMM_ENCODING (0, 0x03, 60), 0XF8000FE7, ARC_OPCODE_ARC64, \ |
|||
STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ |
|||
{ "stdl", STDL_DIMM_ENCODING (0, 0x03, 62), 0xF8000FE7, ARC_OPCODE_ARC64, \ |
|||
STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, |
|||
|
|||
#define STL_ENCODING(DI) ((F32_ST_OFFSET << 27) | (DI << 5) | (0X03 << 1) \ |
|||
| (1)) |
|||
#define MSK_STL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \ |
|||
| (0x03 << 3)))) |
|||
#define STL_ASYM_ENCODING(DI, X) ((F32_ST_OFFSET << 27) | (DI << 5) \ |
|||
| (0X03 << 1) | FIELDB (X) | (1)) |
|||
#define STL_DSYM_ENCODING(X) ((F32_ST_OFFSET << 27) | (0X03 << 1) \ |
|||
| FIELDC (X) | (1)) |
|||
|
|||
/* stl<.aa> c,[b,s9]
|
|||
stl<.aa> w6,[b,s9] |
|||
stl<.as> c,[ximm] |
|||
stl<.as> w6,[ximm] |
|||
stl<.aa> ximm,[b,s9] |
|||
stl<.aa> limm,[b,s9] |
|||
*/ |
|||
#define STL \ |
|||
{ "stl", STL_ENCODING (0), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \ |
|||
{ RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ |
|||
{ "stl", STL_ENCODING (1), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \ |
|||
{ W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ |
|||
{ "stl", STL_ASYM_ENCODING (0, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \ |
|||
{ "stl", STL_ASYM_ENCODING (1, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \ |
|||
{ "stl", STL_ASYM_ENCODING (0, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \ |
|||
{ "stl", STL_ASYM_ENCODING (1, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \ |
|||
{ "stl", STL_DSYM_ENCODING (60), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ |
|||
{ "stl", STL_DSYM_ENCODING (62), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \ |
|||
NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, |
|||
|
|||
/* The opcode table.
|
|||
|
|||
The format of the opcode table is: |
|||
|
|||
NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. |
|||
|
|||
The table is organised such that, where possible, all instructions with |
|||
the same mnemonic are together in a block. When the assembler searches |
|||
for a suitable instruction the entries are checked in table order, so |
|||
more specific, or specialised cases should appear earlier in the table. |
|||
|
|||
As an example, consider two instructions 'add a,b,u6' and 'add |
|||
a,b,limm'. The first takes a 6-bit immediate that is encoded within the |
|||
32-bit instruction, while the second takes a 32-bit immediate that is |
|||
encoded in a follow-on 32-bit, making the total instruction length |
|||
64-bits. In this case the u6 variant must appear first in the table, as |
|||
all u6 immediates could also be encoded using the 'limm' extension, |
|||
however, we want to use the shorter instruction wherever possible. |
|||
|
|||
It is possible though to split instructions with the same mnemonic into |
|||
multiple groups. However, the instructions are still checked in table |
|||
order, even across groups. The only time that instructions with the |
|||
same mnemonic should be split into different groups is when different |
|||
variants of the instruction appear in different architectures, in which |
|||
case, grouping all instructions from a particular architecture together |
|||
might be preferable to merging the instruction into the main instruction |
|||
table. |
|||
|
|||
An example of this split instruction groups can be found with the 'sync' |
|||
instruction. The core arc architecture provides a 'sync' instruction, |
|||
while the nps instruction set extension provides 'sync.rd' and |
|||
'sync.wr'. The rd/wr flags are instruction flags, not part of the |
|||
mnemonic, so we end up with two groups for the sync instruction, the |
|||
first within the core arc instruction table, and the second within the |
|||
nps extension instructions. */ |
|||
|
|||
const struct arc_opcode arc_opcodes[] = |
|||
{ |
|||
|
|||
/* STL and STDL instructions. */ |
|||
STL |
|||
STDL |
|||
|
|||
#include "arc64-tbl.h" |
|||
|
|||
FP_TOP (fhmadd , FMADD , HALF) |
|||
FP_TOP (fhmsub , FMSUB , HALF) |
|||
FP_TOP (fhnmadd, FNMADD, HALF) |
|||
FP_TOP (fhnmsub, FNMSUB, HALF) |
|||
|
|||
FP_TOP (fsmadd , FMADD , SINGLE) |
|||
FP_TOP (fsmsub , FMSUB , SINGLE) |
|||
FP_TOP (fsnmadd, FNMADD, SINGLE) |
|||
FP_TOP (fsnmsub, FNMSUB, SINGLE) |
|||
|
|||
FP_TOP (fdmadd , FMADD , DOUBLE) |
|||
FP_TOP (fdmsub , FMSUB , DOUBLE) |
|||
FP_TOP (fdnmadd, FNMADD, DOUBLE) |
|||
FP_TOP (fdnmsub, FNMSUB, DOUBLE) |
|||
|
|||
/* Vectors. */ |
|||
FP_TOP (vfhmadd , VFMADD , HALF) |
|||
FP_TOP (vfhmsub , VFMSUB , HALF) |
|||
FP_TOP (vfhnmadd, VFNMADD, HALF) |
|||
FP_TOP (vfhnmsub, VFNMSUB, HALF) |
|||
FP_TOP (vfhmadds , VFMADDS , HALF) |
|||
FP_TOP (vfhmsubs , VFMSUBS , HALF) |
|||
FP_TOP (vfhnmadds, VFNMADDS, HALF) |
|||
FP_TOP (vfhnmsubs, VFNMSUBS, HALF) |
|||
|
|||
FP_TOP (vfsmadd , VFMADD , SINGLE) |
|||
FP_TOP (vfsmsub , VFMSUB , SINGLE) |
|||
FP_TOP (vfsnmadd, VFNMADD, SINGLE) |
|||
FP_TOP (vfsnmsub, VFNMSUB, SINGLE) |
|||
FP_TOP (vfsmadds , VFMADDS , SINGLE) |
|||
FP_TOP (vfsmsubs , VFMSUBS , SINGLE) |
|||
FP_TOP (vfsnmadds, VFNMADDS, SINGLE) |
|||
FP_TOP (vfsnmsubs, VFNMSUBS, SINGLE) |
|||
|
|||
FP_TOP_D (vfdmadd , VFMADD , DOUBLE) |
|||
FP_TOP_D (vfdmsub , VFMSUB , DOUBLE) |
|||
FP_TOP_D (vfdnmadd, VFNMADD, DOUBLE) |
|||
FP_TOP_D (vfdnmsub, VFNMSUB, DOUBLE) |
|||
FP_TOP_D (vfdmadds , VFMADDS , DOUBLE) |
|||
FP_TOP_D (vfdmsubs , VFMSUBS , DOUBLE) |
|||
FP_TOP_D (vfdnmadds, VFNMADDS, DOUBLE) |
|||
FP_TOP_D (vfdnmsubs, VFNMSUBS, DOUBLE) |
|||
|
|||
/* 2OPS. */ |
|||
FP_DOP (fhadd , FADD , HALF) |
|||
FP_DOP (fhsub , FSUB , HALF) |
|||
FP_DOP (fhmul , FMUL , HALF) |
|||
FP_DOP (fhdiv , FDIV , HALF) |
|||
FP_DOP (fhmin , FMIN , HALF) |
|||
FP_DOP (fhmax , FMAX , HALF) |
|||
FP_DOP (fhsgnj , FSGNJ , HALF) |
|||
FP_DOP (fhsgnjn, FSGNJN, HALF) |
|||
FP_DOP (fhsgnjx, FSGNJX, HALF) |
|||
|
|||
FP_DOP (fsadd , FADD , SINGLE) |
|||
FP_DOP (fssub , FSUB , SINGLE) |
|||
FP_DOP (fsmul , FMUL , SINGLE) |
|||
FP_DOP (fsdiv , FDIV , SINGLE) |
|||
FP_DOP (fsmin , FMIN , SINGLE) |
|||
FP_DOP (fsmax , FMAX , SINGLE) |
|||
FP_DOP (fssgnj , FSGNJ , SINGLE) |
|||
FP_DOP (fssgnjn, FSGNJN, SINGLE) |
|||
FP_DOP (fssgnjx, FSGNJX, SINGLE) |
|||
|
|||
FP_DOP (fdadd , FADD , DOUBLE) |
|||
FP_DOP (fdsub , FSUB , DOUBLE) |
|||
FP_DOP (fdmul , FMUL , DOUBLE) |
|||
FP_DOP (fddiv , FDIV , DOUBLE) |
|||
FP_DOP (fdmin , FMIN , DOUBLE) |
|||
FP_DOP (fdmax , FMAX , DOUBLE) |
|||
FP_DOP (fdsgnj , FSGNJ , DOUBLE) |
|||
FP_DOP (fdsgnjn, FSGNJN, DOUBLE) |
|||
FP_DOP (fdsgnjx, FSGNJX, DOUBLE) |
|||
|
|||
FP_DOP_C (fhcmp , FCMP , HALF) |
|||
FP_DOP_C (fhcmpf, FCMPF, HALF) |
|||
FP_DOP_C (fscmp , FCMP , SINGLE) |
|||
FP_DOP_C (fscmpf, FCMPF, SINGLE) |
|||
FP_DOP_C (fdcmp , FCMP , DOUBLE) |
|||
FP_DOP_C (fdcmpf, FCMPF, DOUBLE) |
|||
|
|||
/* Vectors. */ |
|||
FP_DOP (vfhadd , VFADD , HALF) |
|||
FP_DOP (vfhsub , VFSUB , HALF) |
|||
FP_DOP (vfhmul , VFMUL , HALF) |
|||
FP_DOP (vfhdiv , VFDIV , HALF) |
|||
FP_DOP (vfhadds, VFADDS, HALF) |
|||
FP_DOP (vfhsubs, VFSUBS, HALF) |
|||
FP_DOP (vfhmuls, VFMULS, HALF) |
|||
FP_DOP (vfhdivs, VFDIVS, HALF) |
|||
|
|||
FP_DOP (vfhunpkl , VFUNPKL , HALF) |
|||
FP_DOP (vfhunpkm , VFUNPKM , HALF) |
|||
FP_DOP (vfhpackl , VFPACKL , HALF) |
|||
FP_DOP (vfhpackm , VFPACKM , HALF) |
|||
FP_DOP (vfhbflyl , VFBFLYL , HALF) |
|||
FP_DOP (vfhbflym , VFBFLYM , HALF) |
|||
FP_DOP (vfhaddsub, VFADDSUB, HALF) |
|||
FP_DOP (vfhsubadd, VFSUBADD, HALF) |
|||
|
|||
FP_DOP (vfsadd , VFADD , SINGLE) |
|||
FP_DOP (vfssub , VFSUB , SINGLE) |
|||
FP_DOP (vfsmul , VFMUL , SINGLE) |
|||
FP_DOP (vfsdiv , VFDIV , SINGLE) |
|||
FP_DOP (vfsadds, VFADDS, SINGLE) |
|||
FP_DOP (vfssubs, VFSUBS, SINGLE) |
|||
FP_DOP (vfsmuls, VFMULS, SINGLE) |
|||
FP_DOP (vfsdivs, VFDIVS, SINGLE) |
|||
|
|||
FP_DOP (vfsunpkl , VFUNPKL , SINGLE) |
|||
FP_DOP (vfsunpkm , VFUNPKM , SINGLE) |
|||
FP_DOP (vfspackl , VFPACKL , SINGLE) |
|||
FP_DOP (vfspackm , VFPACKM , SINGLE) |
|||
FP_DOP (vfsbflyl , VFBFLYL , SINGLE) |
|||
FP_DOP (vfsbflym , VFBFLYM , SINGLE) |
|||
FP_DOP (vfsaddsub, VFADDSUB, SINGLE) |
|||
FP_DOP (vfssubadd, VFSUBADD, SINGLE) |
|||
|
|||
FP_DOP_D (vfdadd , VFADD , DOUBLE) |
|||
FP_DOP_D (vfdsub , VFSUB , DOUBLE) |
|||
FP_DOP_D (vfdmul , VFMUL , DOUBLE) |
|||
FP_DOP_D (vfddiv , VFDIV , DOUBLE) |
|||
FP_DOP_D (vfdadds, VFADDS, DOUBLE) |
|||
FP_DOP_D (vfdsubs, VFSUBS, DOUBLE) |
|||
FP_DOP_D (vfdmuls, VFMULS, DOUBLE) |
|||
FP_DOP_D (vfddivs, VFDIVS, DOUBLE) |
|||
|
|||
FP_DOP_D (vfdunpkl , VFUNPKL , DOUBLE) |
|||
FP_DOP_D (vfdunpkm , VFUNPKM , DOUBLE) |
|||
FP_DOP_D (vfdpackl , VFPACKL , DOUBLE) |
|||
FP_DOP_D (vfdpackm , VFPACKM , DOUBLE) |
|||
FP_DOP_D (vfdbflyl , VFBFLYL , DOUBLE) |
|||
FP_DOP_D (vfdbflym , VFBFLYM , DOUBLE) |
|||
FP_DOP_D (vfdaddsub, VFADDSUB, DOUBLE) |
|||
FP_DOP_D (vfdsubadd, VFSUBADD, DOUBLE) |
|||
|
|||
FP_SOP (fhsqrt, FSQRT, HALF) |
|||
FP_SOP (fssqrt, FSQRT, SINGLE) |
|||
FP_SOP (fdsqrt, FSQRT, DOUBLE) |
|||
FP_SOP (vfhsqrt, VFSQRT, HALF) |
|||
FP_SOP (vfssqrt, VFSQRT, SINGLE) |
|||
FP_SOP_D (vfdsqrt, VFSQRT,DOUBLE) |
|||
|
|||
FP_SOP (vfhexch, VFEXCH, HALF) |
|||
FP_SOP (vfsexch, VFEXCH, SINGLE) |
|||
FP_SOP_D (vfdexch, VFEXCH, DOUBLE) |
|||
|
|||
FP_COP (fhmov, FMOV, HALF) |
|||
FP_COP (fsmov, FMOV, SINGLE) |
|||
FP_COP (fdmov, FMOV, DOUBLE) |
|||
FP_COP (vfhmov, VFMOV, HALF) |
|||
FP_COP (vfsmov, VFMOV, SINGLE) |
|||
FP_COP (vfdmov, VFMOV, DOUBLE) |
|||
|
|||
FP_CVI2F (fuint2s, FUINT2S, 0x00) |
|||
FP_CVI2F (fuint2d, FUINT2D, 0x00) |
|||
FP_CVI2F (ful2s, FUL2S, 0x00) |
|||
FP_CVI2F (ful2d, FUL2D, 0x00) |
|||
|
|||
FP_CVF2I (fs2uint, FS2UINT, 0x01) |
|||
FP_CVF2I (fs2ul, FS2UL, 0x01) |
|||
FP_CVF2I (fd2uint, FD2UINT, 0x01) |
|||
FP_CVF2I (fd2ul, FD2UL, 0x01) |
|||
|
|||
FP_CVI2F (fint2s, FINT2S, 0x02) |
|||
FP_CVI2F (fint2d, FINT2D, 0x02) |
|||
FP_CVI2F (fl2s, FL2S, 0x02) |
|||
FP_CVI2F (fl2d, FL2D, 0x02) |
|||
|
|||
FP_CVF2I (fs2int, FS2INT, 0x03) |
|||
FP_CVF2I (fs2l, FS2L, 0x03) |
|||
FP_CVF2I (fd2int, FD2INT, 0x03) |
|||
FP_CVF2I (fd2l, FD2L, 0x03) |
|||
|
|||
FP_CVF2F (fs2d, FS2D, 0x04) |
|||
FP_CVF2F (fd2s, FD2S, 0x04) |
|||
|
|||
FP_RND (fsrnd, FSRND, 0x06) |
|||
FP_RND (fdrnd, FDRND, 0x06) |
|||
|
|||
FP_CVF2I (fs2uint_rz, F2UINT_RZ, 0x09) |
|||
FP_CVF2I (fs2ul_rz, FS2UL_RZ, 0x09) |
|||
FP_CVF2I (fd2uint_rz, FD2UINT_RZ, 0x09) |
|||
FP_CVF2I (fd2ul_rz, FD2UL_RZ, 0x09) |
|||
|
|||
FP_CVF2I (fs2int_rz, FSINT_RZ, 0x0B) |
|||
FP_CVF2I (fs2l_rz, FS2L_RZ, 0x0B) |
|||
FP_CVF2I (fd2int_rz, FD2INT_RZ, 0x0B) |
|||
FP_CVF2I (fd2l_rz, FD2L_RZ, 0x0B) |
|||
|
|||
FP_RND (fsrnd_rz, FSRND_RZ, 0x0E) |
|||
FP_RND (fdrnd_rz, FDRND_RZ, 0x0E) |
|||
|
|||
FMVI2F (fmvi2s, FMVI2S, 0x10) |
|||
FMVI2F (fmvl2d, FMVL2D, 0x10) |
|||
|
|||
FMVF2I (fmvs2i, FMVS2I, 0x11) |
|||
FMVF2I (fmvd2l, FMVD2L, 0x11) |
|||
|
|||
FP_CVF2F (fs2h, FS2H, 0x14) |
|||
FP_CVF2F (fh2s, FH2S, 0x15) |
|||
FP_CVF2F (fs2h_rz, FS2H_RZ, 0x1C) |
|||
|
|||
FP_LOAD (fld16, 0x02, 0) |
|||
FP_LOAD (fld32, 0x00, 0) |
|||
FP_LOAD (fld64, 0x01, 0) |
|||
FP_LOAD (fldd32, 0x00, 1) |
|||
FP_LOAD (fldd64, 0x01, 1) |
|||
|
|||
FP_STORE (fst16, 0x02, 0) |
|||
FP_STORE (fst32, 0x00, 0) |
|||
FP_STORE (fst64, 0x01, 0) |
|||
FP_STORE (fstd32, 0x00, 1) |
|||
FP_STORE (fstd64, 0x01, 1) |
|||
|
|||
FP_EXT (vfhext, HALF) |
|||
FP_EXT (vfsext, SINGLE) |
|||
FP_EXT (vfdext, DOUBLE) |
|||
|
|||
FP_INS (vfhins, HALF) |
|||
FP_INS (vfsins, SINGLE) |
|||
FP_INS (vfdins, DOUBLE) |
|||
|
|||
FP_REP (vfhrep, HALF) |
|||
FP_REP (vfsrep, SINGLE) |
|||
FP_REP (vfdrep, DOUBLE) |
|||
|
|||
#undef FLAGS_F |
|||
#define FLAGS_F { 0 } |
|||
|
|||
#undef FLAGS_CCF |
|||
#define FLAGS_CCF { C_CC } |
|||
|
|||
#undef FIELDF |
|||
#define FIELDF 0x0 |
|||
|
|||
EXTINSN3OP ("vmin2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x11) |
|||
EXTINSN3OP ("vmax2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x0b) |
|||
|
|||
#undef HARD_FIELDF |
|||
#define HARD_FIELDF (0x01 << 15) |
|||
|
|||
EXTINSN3OP ("vmin2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x38) |
|||
EXTINSN3OP ("vmax2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x39) |
|||
|
|||
EXTINSN3OP ("vpack4hl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x30) |
|||
EXTINSN3OP ("vpack4hm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x31) |
|||
EXTINSN3OP ("vpack2wl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x32) |
|||
EXTINSN3OP ("vpack2wm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x33) |
|||
EXTINSN3OP ("vpack2hm", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, |
|||
F32_EXT5, 0x29) |
|||
|
|||
#undef HARD_FIELDF |
|||
#define HARD_FIELDF (0x0) |
|||
|
|||
OP64INSN3OP ("mpyl", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x30) |
|||
OP64INSN3OP ("mpyml", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x31) |
|||
OP64INSN3OP ("mpymul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x32) |
|||
OP64INSN3OP ("mpymsul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x33) |
|||
|
|||
EXTINSN3OP ("vpack2hl", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, |
|||
F32_EXT5, 0x29) |
|||
|
|||
{ NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } |
|||
}; |
|||
File diff suppressed because it is too large
Loading…
Reference in new issue