|
|
|
@ -2348,6 +2348,9 @@ extract_vleil (unsigned long insn, |
|
|
|
/* The mask for an VA form instruction. */ |
|
|
|
#define VXA_MASK VXA(0x3f, 0x3f) |
|
|
|
|
|
|
|
/* A VXA_MASK with a SHB field. */ |
|
|
|
#define VXASHB_MASK (VXA_MASK | (1 << 10)) |
|
|
|
|
|
|
|
/* A VXR form instruction. */ |
|
|
|
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
|
|
|
|
|
|
|
@ -2837,7 +2840,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
|
|
|
{"vsel", VXA(4, 42), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
|
|
|
{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, |
|
|
|
{"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, |
|
|
|
{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}}, |
|
|
|
{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}}, |
|
|
|
{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, |
|
|
|
{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, |
|
|
|
{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, |
|
|
|
|