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@ -25,8 +25,12 @@ |
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#include <assert.h> |
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#include "dis-asm.h" |
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#include "opcode/arc.h" |
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#include "elf/arc.h" |
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#include "arc-dis.h" |
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#include "arc-ext.h" |
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#include "elf-bfd.h" |
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#include "libiberty.h" |
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#include "opintl.h" |
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/* Structure used to iterate over, and extract the values for, operands of
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an opcode. */ |
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@ -81,6 +85,20 @@ static const char * const regnames[64] = |
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"r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl" |
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}; |
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/* This structure keeps track which instruction class(es)
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should be ignored durring disassembling. */ |
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typedef struct skipclass |
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{ |
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insn_class_t insn_class; |
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insn_subclass_t subclass; |
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struct skipclass *nxt; |
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} skipclass_t, *linkclass; |
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/* Intial classes of instructions to be consider first when
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disassembling. */ |
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static linkclass decodelist = NULL; |
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/* Macros section. */ |
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#ifdef DEBUG |
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@ -101,6 +119,88 @@ static const char * const regnames[64] = |
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/* Functions implementation. */ |
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/* Return TRUE when two classes are not opcode conflicting. */ |
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static bfd_boolean |
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is_compatible_p (insn_class_t classA, |
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insn_subclass_t sclassA, |
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insn_class_t classB, |
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insn_subclass_t sclassB) |
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{ |
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if (classA == DSP && sclassB == DPX) |
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return FALSE; |
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if (sclassA == DPX && classB == DSP) |
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return FALSE; |
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return TRUE; |
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} |
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/* Add a new element to the decode list. */ |
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static void |
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add_to_decodelist (insn_class_t insn_class, |
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insn_subclass_t subclass) |
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{ |
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linkclass t = (linkclass) xmalloc (sizeof (skipclass_t)); |
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t->insn_class = insn_class; |
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t->subclass = subclass; |
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t->nxt = decodelist; |
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decodelist = t; |
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} |
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/* Return TRUE if we need to skip the opcode from being
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disassembled. */ |
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static bfd_boolean |
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skip_this_opcode (const struct arc_opcode * opcode, |
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struct disassemble_info * info) |
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{ |
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linkclass t = decodelist; |
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bfd_boolean addme = TRUE; |
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/* Check opcode for major 0x06, return if it is not in. */ |
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if (OPCODE (opcode->opcode) != 0x06) |
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return FALSE; |
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while (t != NULL |
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&& is_compatible_p (t->insn_class, t->subclass, |
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opcode->insn_class, opcode->subclass)) |
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{ |
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if ((t->insn_class == opcode->insn_class) |
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&& (t->subclass == opcode->subclass)) |
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addme = FALSE; |
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t = t->nxt; |
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} |
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/* If we found an incompatibility then we must skip. */ |
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if (t != NULL) |
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return TRUE; |
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/* Even if we do not precisely know the if the right mnemonics
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is correctly displayed, keep the disassmbled code class |
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consistent. */ |
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if (addme) |
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{ |
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switch (opcode->insn_class) |
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{ |
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case DSP: |
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case FLOAT: |
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/* Add to the conflict list only the classes which
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counts. */ |
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add_to_decodelist (opcode->insn_class, opcode->subclass); |
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/* Warn if we have to decode an opcode and no preferred
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classes have been chosen. */ |
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info->fprintf_func (info->stream, _("\n\
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Warning: disassembly may be wrong due to guessed opcode class choice.\n\ |
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Use -M<class[,class]> to select the correct opcode class(es).\n\t\t\t\t")); |
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break; |
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default: |
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break; |
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} |
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} |
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return FALSE; |
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} |
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static bfd_vma |
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bfd_getm32 (unsigned int data) |
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{ |
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@ -111,7 +211,7 @@ bfd_getm32 (unsigned int data) |
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return value; |
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} |
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static int |
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static bfd_boolean |
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special_flag_p (const char *opname, |
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const char *flgname) |
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{ |
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@ -133,124 +233,137 @@ special_flag_p (const char *opname, |
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break; /* End of the array. */ |
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if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0) |
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return 1; |
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return TRUE; |
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} |
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} |
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return 0; |
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return FALSE; |
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} |
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/* Find opcode from ARC_TABLE given the instruction described by INSN and
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INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */ |
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static const struct arc_opcode * |
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find_format_from_table (const struct arc_opcode *arc_table, |
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unsigned *insn, unsigned int insn_len, |
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unsigned isa_mask, bfd_boolean *has_limm) |
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find_format_from_table (struct disassemble_info *info, |
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const struct arc_opcode *arc_table, |
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unsigned *insn, |
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unsigned int insn_len, |
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unsigned isa_mask, |
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bfd_boolean *has_limm, |
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bfd_boolean overlaps) |
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{ |
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unsigned int i = 0; |
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const struct arc_opcode *opcode = NULL; |
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const unsigned char *opidx; |
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const unsigned char *flgidx; |
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do { |
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bfd_boolean invalid = FALSE; |
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do |
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{ |
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bfd_boolean invalid = FALSE; |
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opcode = &arc_table[i++]; |
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opcode = &arc_table[i++]; |
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if (ARC_SHORT (opcode->mask) && (insn_len == 2)) |
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{ |
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0])) |
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continue; |
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} |
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else if (!ARC_SHORT (opcode->mask) && (insn_len == 4)) |
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{ |
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if (OPCODE (opcode->opcode) != OPCODE (insn[0])) |
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continue; |
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} |
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else |
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continue; |
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if (ARC_SHORT (opcode->mask) && (insn_len == 2)) |
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{ |
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0])) |
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continue; |
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} |
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else if (!ARC_SHORT (opcode->mask) && (insn_len == 4)) |
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{ |
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if (OPCODE (opcode->opcode) != OPCODE (insn[0])) |
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continue; |
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} |
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else |
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continue; |
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if ((insn[0] ^ opcode->opcode) & opcode->mask) |
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continue; |
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if ((insn[0] ^ opcode->opcode) & opcode->mask) |
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continue; |
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if (!(opcode->cpu & isa_mask)) |
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continue; |
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if (!(opcode->cpu & isa_mask)) |
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continue; |
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*has_limm = FALSE; |
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*has_limm = FALSE; |
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/* Possible candidate, check the operands. */ |
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for (opidx = opcode->operands; *opidx; opidx++) |
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{ |
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int value; |
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const struct arc_operand *operand = &arc_operands[*opidx]; |
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/* Possible candidate, check the operands. */ |
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for (opidx = opcode->operands; *opidx; opidx++) |
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{ |
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int value; |
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const struct arc_operand *operand = &arc_operands[*opidx]; |
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if (operand->flags & ARC_OPERAND_FAKE) |
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continue; |
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if (operand->flags & ARC_OPERAND_FAKE) |
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continue; |
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if (operand->extract) |
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value = (*operand->extract) (insn[0], &invalid); |
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else |
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); |
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/* Check for LIMM indicator. If it is there, then make sure
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we pick the right format. */ |
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if (operand->flags & ARC_OPERAND_IR |
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&& !(operand->flags & ARC_OPERAND_LIMM)) |
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{ |
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if ((value == 0x3E && insn_len == 4) |
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|| (value == 0x1E && insn_len == 2)) |
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{ |
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invalid = TRUE; |
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break; |
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} |
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} |
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if (operand->flags & ARC_OPERAND_LIMM |
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&& !(operand->flags & ARC_OPERAND_DUPLICATE)) |
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*has_limm = TRUE; |
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} |
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/* Check the flags. */ |
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for (flgidx = opcode->flags; *flgidx; flgidx++) |
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{ |
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/* Get a valid flag class. */ |
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; |
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const unsigned *flgopridx; |
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int foundA = 0, foundB = 0; |
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unsigned int value; |
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/* Check first the extensions. */ |
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if (cl_flags->flag_class & F_CLASS_EXTEND) |
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{ |
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value = (insn[0] & 0x1F); |
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if (arcExtMap_condCodeName (value)) |
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continue; |
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} |
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) |
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{ |
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const struct arc_flag_operand *flg_operand = |
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&arc_flag_operands[*flgopridx]; |
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value = (insn[0] >> flg_operand->shift) |
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& ((1 << flg_operand->bits) - 1); |
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if (value == flg_operand->code) |
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foundA = 1; |
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if (value) |
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foundB = 1; |
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} |
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if (!foundA && foundB) |
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{ |
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invalid = TRUE; |
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break; |
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} |
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} |
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if (invalid) |
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continue; |
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/* The instruction is valid. */ |
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return opcode; |
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} while (opcode->mask); |
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if (operand->extract) |
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value = (*operand->extract) (insn[0], &invalid); |
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else |
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); |
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/* Check for LIMM indicator. If it is there, then make sure
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we pick the right format. */ |
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if (operand->flags & ARC_OPERAND_IR |
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&& !(operand->flags & ARC_OPERAND_LIMM)) |
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{ |
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if ((value == 0x3E && insn_len == 4) |
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|| (value == 0x1E && insn_len == 2)) |
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{ |
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invalid = TRUE; |
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break; |
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} |
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} |
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if (operand->flags & ARC_OPERAND_LIMM |
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&& !(operand->flags & ARC_OPERAND_DUPLICATE)) |
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*has_limm = TRUE; |
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} |
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/* Check the flags. */ |
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for (flgidx = opcode->flags; *flgidx; flgidx++) |
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{ |
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/* Get a valid flag class. */ |
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; |
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const unsigned *flgopridx; |
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int foundA = 0, foundB = 0; |
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unsigned int value; |
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/* Check first the extensions. */ |
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if (cl_flags->flag_class & F_CLASS_EXTEND) |
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{ |
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value = (insn[0] & 0x1F); |
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if (arcExtMap_condCodeName (value)) |
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continue; |
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} |
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) |
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{ |
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const struct arc_flag_operand *flg_operand = |
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&arc_flag_operands[*flgopridx]; |
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value = (insn[0] >> flg_operand->shift) |
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& ((1 << flg_operand->bits) - 1); |
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if (value == flg_operand->code) |
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foundA = 1; |
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if (value) |
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foundB = 1; |
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} |
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if (!foundA && foundB) |
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{ |
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invalid = TRUE; |
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break; |
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} |
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} |
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if (invalid) |
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continue; |
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if (insn_len == 4 |
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&& overlaps |
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&& skip_this_opcode (opcode, info)) |
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continue; |
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/* The instruction is valid. */ |
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return opcode; |
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} |
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while (opcode->mask); |
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return NULL; |
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} |
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@ -344,44 +457,42 @@ find_format_long_instructions (unsigned *insn, |
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the opcode's operands. */ |
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static bfd_boolean |
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find_format (bfd_vma memaddr, unsigned *insn, unsigned int *insn_len, |
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unsigned isa_mask, struct disassemble_info *info, |
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const struct arc_opcode **opcode_result, |
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struct arc_operand_iterator *iter) |
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find_format (bfd_vma memaddr, |
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unsigned * insn, |
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unsigned int * insn_len, |
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unsigned isa_mask, |
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struct disassemble_info * info, |
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const struct arc_opcode ** opcode_result, |
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struct arc_operand_iterator * iter) |
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{ |
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const struct arc_opcode *opcode; |
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const struct arc_opcode *opcode = NULL; |
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bfd_boolean needs_limm; |
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const extInstruction_t *einsn; |
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/* Find the first match in the opcode table. */ |
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opcode = find_format_from_table (arc_opcodes, insn, *insn_len, |
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isa_mask, &needs_limm); |
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if (opcode == NULL) |
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/* First, try the extension instructions. */ |
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einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]); |
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if (einsn != NULL) |
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{ |
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const extInstruction_t *einsn; |
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const char *errmsg = NULL; |
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/* No instruction found. Try the extensions. */ |
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einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]); |
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if (einsn != NULL) |
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opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg); |
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if (opcode == NULL) |
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{ |
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const char *errmsg = NULL; |
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opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg); |
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if (opcode == NULL) |
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{ |
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(*info->fprintf_func) (info->stream, |
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"An error occured while " |
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"generating the extension instruction " |
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"operations"); |
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*opcode_result = NULL; |
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return FALSE; |
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} |
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opcode = find_format_from_table (opcode, insn, *insn_len, |
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isa_mask, &needs_limm); |
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assert (opcode != NULL); |
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(*info->fprintf_func) (info->stream, "\
|
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An error occured while generating the extension instruction operations"); |
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*opcode_result = NULL; |
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return FALSE; |
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} |
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opcode = find_format_from_table (info, opcode, insn, *insn_len, |
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isa_mask, &needs_limm, FALSE); |
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} |
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/* Then, try finding the first match in the opcode table. */ |
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if (opcode == NULL) |
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opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len, |
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isa_mask, &needs_limm, TRUE); |
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|
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if (needs_limm && opcode != NULL) |
|
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{ |
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bfd_byte buffer[4]; |
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@ -697,6 +808,65 @@ operand_iterator_next (struct arc_operand_iterator *iter, |
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return TRUE; |
|
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} |
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|
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/* Helper for parsing the options. */ |
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static void |
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parse_option (char *option) |
|
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{ |
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if (CONST_STRNEQ (option, "dsp")) |
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add_to_decodelist (DSP, NONE); |
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|
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else if (CONST_STRNEQ (option, "spfp")) |
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add_to_decodelist (FLOAT, SPX); |
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else if (CONST_STRNEQ (option, "dpfp")) |
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add_to_decodelist (FLOAT, DPX); |
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else if (CONST_STRNEQ (option, "quarkse_em")) |
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add_to_decodelist (FLOAT, QUARKSE); |
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else if (CONST_STRNEQ (option, "fpuda")) |
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add_to_decodelist (FLOAT, DPA); |
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else if (CONST_STRNEQ (option, "fpud")) |
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|
{ |
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|
add_to_decodelist (FLOAT, SP); |
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|
add_to_decodelist (FLOAT, CVT); |
|
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|
} |
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else if (CONST_STRNEQ (option, "fpus")) |
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|
{ |
|
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|
add_to_decodelist (FLOAT, DP); |
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|
add_to_decodelist (FLOAT, CVT); |
|
|
|
} |
|
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|
else |
|
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|
fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); |
|
|
|
} |
|
|
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|
|
|
|
/* Go over the options list and parse it. */ |
|
|
|
|
|
|
|
static void |
|
|
|
parse_disassembler_options (char *options) |
|
|
|
{ |
|
|
|
if (options == NULL) |
|
|
|
return; |
|
|
|
|
|
|
|
while (*options) |
|
|
|
{ |
|
|
|
/* Skip empty options. */ |
|
|
|
if (*options == ',') |
|
|
|
{ |
|
|
|
++ options; |
|
|
|
continue; |
|
|
|
} |
|
|
|
|
|
|
|
parse_option (options); |
|
|
|
|
|
|
|
while (*options != ',' && *options != '\0') |
|
|
|
++ options; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
/* Disassemble ARC instructions. */ |
|
|
|
|
|
|
|
static int |
|
|
|
@ -716,11 +886,23 @@ print_insn_arc (bfd_vma memaddr, |
|
|
|
const struct arc_operand *operand; |
|
|
|
int value; |
|
|
|
struct arc_operand_iterator iter; |
|
|
|
Elf_Internal_Ehdr *header = NULL; |
|
|
|
|
|
|
|
if (info->disassembler_options) |
|
|
|
{ |
|
|
|
parse_disassembler_options (info->disassembler_options); |
|
|
|
|
|
|
|
/* Avoid repeated parsing of the options. */ |
|
|
|
info->disassembler_options = NULL; |
|
|
|
} |
|
|
|
|
|
|
|
memset (&iter, 0, sizeof (iter)); |
|
|
|
lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0); |
|
|
|
highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1); |
|
|
|
|
|
|
|
if (info->section && info->section->owner) |
|
|
|
header = elf_elfheader (info->section->owner); |
|
|
|
|
|
|
|
switch (info->mach) |
|
|
|
{ |
|
|
|
case bfd_mach_arc_arc700: |
|
|
|
@ -733,7 +915,15 @@ print_insn_arc (bfd_vma memaddr, |
|
|
|
|
|
|
|
case bfd_mach_arc_arcv2: |
|
|
|
default: |
|
|
|
isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM; |
|
|
|
isa_mask = ARC_OPCODE_ARCv2EM; |
|
|
|
if ((header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS) |
|
|
|
{ |
|
|
|
isa_mask = ARC_OPCODE_ARCv2HS; |
|
|
|
/* FPU instructions are not extensions for HS. */ |
|
|
|
add_to_decodelist (FLOAT, SP); |
|
|
|
add_to_decodelist (FLOAT, DP); |
|
|
|
add_to_decodelist (FLOAT, CVT); |
|
|
|
} |
|
|
|
break; |
|
|
|
} |
|
|
|
|
|
|
|
@ -810,6 +1000,7 @@ print_insn_arc (bfd_vma memaddr, |
|
|
|
|
|
|
|
insn_len = arc_insn_length (buffer[lowbyte], buffer[highbyte], info); |
|
|
|
pr_debug ("instruction length = %d bytes\n", insn_len); |
|
|
|
|
|
|
|
switch (insn_len) |
|
|
|
{ |
|
|
|
case 2: |
|
|
|
@ -1042,6 +1233,30 @@ arcAnalyzeInstr (bfd_vma memaddr, |
|
|
|
return ret; |
|
|
|
} |
|
|
|
|
|
|
|
void |
|
|
|
print_arc_disassembler_options (FILE *stream) |
|
|
|
{ |
|
|
|
fprintf (stream, _("\n\
|
|
|
|
The following ARC specific disassembler options are supported for use \n\ |
|
|
|
with -M switch (multiple options should be separated by commas):\n")); |
|
|
|
|
|
|
|
fprintf (stream, _("\
|
|
|
|
dsp Recognize DSP instructions.\n")); |
|
|
|
fprintf (stream, _("\
|
|
|
|
spfp Recognize FPX SP instructions.\n")); |
|
|
|
fprintf (stream, _("\
|
|
|
|
dpfp Recognize FPX DP instructions.\n")); |
|
|
|
fprintf (stream, _("\
|
|
|
|
quarkse_em Recognize FPU QuarkSE-EM instructions.\n")); |
|
|
|
fprintf (stream, _("\
|
|
|
|
fpuda Recognize double assist FPU instructions.\n")); |
|
|
|
fprintf (stream, _("\
|
|
|
|
fpus Recognize single precision FPU instructions.\n")); |
|
|
|
fprintf (stream, _("\
|
|
|
|
fpud Recognize double precision FPU instructions.\n")); |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
/* Local variables:
|
|
|
|
eval: (c-set-style "gnu") |
|
|
|
indent-tabs-mode: t |
|
|
|
|
Claudiu Zissulescu
10 years ago
Nick Clifton