Browse Source
Written by matthew green <mrg@redhat.com>, with fixes from Aldy Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and Nick Clifton <nickc@redhat.com>. * ppc-instructions: Include altivec.igen and e500.igen. (model_busy, model_data): Add vr_busy and vscr_busy. (model_trace_release): Trace vr_busy and vscr_busy. (model_new_cycle): Update vr_busy and vscr_busy. (model_make_busy): Update vr_busy and vscr_busy. * registers.c (register_description): Add Altivec and e500 registers. * psim.c (psim_read_register, psim_read_register): Handle Altivec and e500 registers. * ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers. * configure.in (sim_filter): When *altivec* add "av". When *spe* or *simd* add e500. (sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add WITH_E500. * configure: Re-generate. * e500.igen, altivec.igen: New files. * e500_expression.h, altivec_expression.h: New files. * idecode_expression.h: Update copyright. Include "e500_expression.h" and "altivec_expression.h". * e500_registers.h, altivec_registers.h: New files. * registers.h: Update copyright. Include "e500_registers.h" and "altivec_registers.h". (registers): Add Altivec and e500 specific registers. * Makefile.in (IDECODE_H): Add "idecode_e500.h" and "idecode_altivec.h". (REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h". (tmp-igen): Add dependencies on altivec.igen and e500.igen .ezannoni_pie-20030916-branch
Andrew Cagney
23 years ago
16 changed files with 6387 additions and 99 deletions
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/* Altivec expression macros, for PSIM, the PowerPC simulator.
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Copyright 2003 Free Software Foundation, Inc. |
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Contributed by Red Hat Inc; developed under contract from Motorola. |
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Written by matthew green <mrg@redhat.com>. |
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This file is part of GDB. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, |
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Boston, MA 02111-1307, USA. */ |
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/* AltiVec macro helpers. */ |
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#define ALTIVEC_SET_CR6(vS, checkone) \ |
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do { \ |
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if (checkone && ((*vS).w[0] == 0xffffffff && \ |
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(*vS).w[1] == 0xffffffff && \ |
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(*vS).w[2] == 0xffffffff && \ |
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(*vS).w[3] == 0xffffffff)) \ |
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CR_SET(6, 1 << 3); \ |
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else if ((*vS).w[0] == 0 && \ |
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(*vS).w[1] == 0 && \ |
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(*vS).w[2] == 0 && \ |
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(*vS).w[3] == 0) \ |
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CR_SET(6, 1 << 1); \ |
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else \ |
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CR_SET(6, 0); \ |
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} while (0) |
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#define VSCR_SAT 0x00000001 |
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#define VSCR_NJ 0x00010000 |
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#define ALTIVEC_SET_SAT(sat) \ |
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do { \ |
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if (sat) \ |
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VSCR |= VSCR_SAT; \ |
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} while (0) |
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@ -0,0 +1,63 @@ |
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/* Altivec registers, for PSIM, the PowerPC simulator.
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Copyright 2003 Free Software Foundation, Inc. |
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Contributed by Red Hat Inc; developed under contract from Motorola. |
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Written by matthew green <mrg@redhat.com>. |
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This file is part of GDB. |
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|
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, |
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Boston, MA 02111-1307, USA. */ |
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/* Manage this as 4 32-bit entities, 8 16-bit entities or 16 8-bit
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entities. */ |
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typedef union |
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{ |
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unsigned8 b[16]; |
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unsigned16 h[8]; |
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unsigned32 w[4]; |
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} vreg; |
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typedef unsigned32 vscreg; |
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struct altivec_regs { |
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/* AltiVec Registers */ |
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vreg vr[32]; |
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vscreg vscr; |
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}; |
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/* AltiVec registers */ |
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#define VR(N) cpu_registers(processor)->altivec.vr[N] |
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/* AltiVec vector status and control register */ |
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#define VSCR cpu_registers(processor)->altivec.vscr |
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/* AltiVec endian helpers, wrong endian hosts vs targets need to be
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sure to get the right bytes/halfs/words when the order matters. |
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Note that many AltiVec instructions do not depend on byte order and |
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work on N independant bits of data. This is only for the |
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instructions that actually move data around. */ |
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#if (WITH_HOST_BYTE_ORDER == BIG_ENDIAN) |
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#define AV_BINDEX(x) ((x) & 15) |
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#define AV_HINDEX(x) ((x) & 7) |
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#else |
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static char endian_b2l_bindex[16] = { 3, 2, 1, 0, 7, 6, 5, 4, |
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11, 10, 9, 8, 15, 14, 13, 12 }; |
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static char endian_b2l_hindex[16] = { 1, 0, 3, 2, 5, 4, 7, 6 }; |
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#define AV_BINDEX(x) endian_b2l_bindex[(x) & 15] |
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#define AV_HINDEX(x) endian_b2l_hindex[(x) & 7] |
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#endif |
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/* e500 expression macros, for PSIM, the PowerPC simulator.
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Copyright 2003 Free Software Foundation, Inc. |
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Contributed by Red Hat Inc; developed under contract from Motorola. |
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Written by matthew green <mrg@redhat.com>. |
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This file is part of GDB. |
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|
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, |
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Boston, MA 02111-1307, USA. */ |
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/* e500 register dance */ |
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#define EV_SET_REG4(sh, sl, h0, h1, h2, h3) do { \ |
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(sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \ |
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(sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \ |
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} while (0) |
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#define EV_SET_REG4_ACC(sh, sl, h0, h1, h2, h3) do { \ |
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(sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \ |
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(sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \ |
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ACC = ((unsigned64)(sh) << 32) | (sl & 0xffffffff); \ |
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} while (0) |
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#define EV_SET_REG2(sh, sl, dh, dl) do { \ |
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(sh) = (dh) & 0xffffffff; \ |
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(sl) = (dl) & 0xffffffff; \ |
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} while (0) |
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#define EV_SET_REG2_ACC(sh, sl, dh, dl) do { \ |
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(sh) = (dh) & 0xffffffff; \ |
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(sl) = (dl) & 0xffffffff; \ |
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ACC = ((unsigned64)(sh) << 32) | ((sl) & 0xffffffff); \ |
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} while (0) |
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#define EV_SET_REG1(sh, sl, d) do { \ |
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(sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \ |
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(sl) = (d) & 0xffffffff; \ |
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} while (0) |
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#define EV_SET_REG1_ACC(sh, sl, d) do { \ |
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(sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \ |
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(sl) = (d) & 0xffffffff; \ |
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ACC = (d); \ |
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} while (0) |
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#define EV_SET_REG(s, d) do { \ |
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(s) = (d) & 0xffffffff; \ |
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} while (0) |
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/* get the low or high half word of a word */ |
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#define EV_LOHALF(x) ((unsigned32)(x) & 0xffff) |
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#define EV_HIHALF(x) (((unsigned32)(x) >> 16) & 0xffff) |
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/* partially visible accumulator accessors */ |
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#define EV_SET_ACC(rh, rl) \ |
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ACC = ((unsigned64)(rh) << 32) | ((rl) & 0xffffffff) |
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#define EV_ACCLOW (ACC & 0xffffffff) |
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#define EV_ACCHIGH ((ACC >> 32) & 0xffffffff) |
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/* bit manipulation macros needed for e500 SPE */ |
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#define EV_BITREVERSE16(x) \ |
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(((x) & 0x0001) << 15) \ |
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| (((x) & 0x0002) << 13) \ |
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| (((x) & 0x0004) << 11) \ |
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| (((x) & 0x0008) << 9) \ |
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| (((x) & 0x0010) << 7) \ |
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| (((x) & 0x0020) << 5) \ |
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| (((x) & 0x0040) << 3) \ |
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| (((x) & 0x0080) << 1) \ |
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| (((x) & 0x0100) >> 1) \ |
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| (((x) & 0x0200) >> 3) \ |
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| (((x) & 0x0400) >> 5) \ |
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| (((x) & 0x0800) >> 7) \ |
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| (((x) & 0x1000) >> 9) \ |
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| (((x) & 0x2000) >> 11) \ |
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| (((x) & 0x4000) >> 13) \ |
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| (((x) & 0x8000) >> 15) |
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/* saturation helpers */ |
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#define EV_MUL16_SSF(a,b) ((signed64)((signed32)(signed16)(a) * (signed32)(signed16)(b)) << 1) |
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/* this one loses the top sign bit; be careful */ |
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#define EV_MUL32_SSF(a,b) (((signed64)(signed32)(a) * (signed64)(signed32)(b)) << 1) |
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#define EV_SAT_P_S32(x) ((((signed64)(x)) < -0x80000000LL) || (((signed64)(x)) > 0x7fffffffLL)) |
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#define EV_SAT_P_U32(x) ((((signed64)(x)) < -0LL) || (((signed64)(x)) > 0xffffffffLL)) |
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#define EV_SATURATE(flag, sat_val, val) \ |
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((flag) ? (sat_val) : (val)) |
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#define EV_SATURATE_ACC(flag, sign, negative_sat_val, positive_sat_val, val) \ |
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((flag) ? ((((sign) >> 63) & 1) ? (negative_sat_val) : (positive_sat_val)) : (val)) |
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/* SPEFSCR handling. */ |
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/* These bits must be clear. */ |
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#define EV_SPEFSCR_MASK (BIT(40) | BIT(41) | spefscr_mode | BIT(56)) |
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/* The Inexact and Divide by zero sticky bits are based on others. */ |
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#define EV_SET_SPEFSCR(bits) do { \ |
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int finxs = (bits) & (spefscr_fgh|spefscr_fxh|spefscr_fg|spefscr_fx); \ |
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int fdbzs = (bits) & (spefscr_fdbzh|spefscr_fdbz); \ |
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SPREG(spr_spefscr) = ((bits) & ~EV_SPEFSCR_MASK) | \ |
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(finxs ? spefscr_finxs : 0) | \ |
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(fdbzs ? spefscr_fdbzs : 0); \ |
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} while (0) |
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#define EV_SET_SPEFSCR_BITS(s) \ |
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EV_SET_SPEFSCR(SPREG(spr_spefscr) | (s)) |
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#define EV_SET_SPEFSCR_OV(l,h) do { \ |
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unsigned32 _sPefScR = SPREG(spr_spefscr); \ |
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if (l) \ |
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_sPefScR |= spefscr_ov | spefscr_sov; \ |
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else \ |
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_sPefScR &= ~spefscr_ov; \ |
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if (h) \ |
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_sPefScR |= spefscr_ovh | spefscr_sovh; \ |
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else \ |
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_sPefScR &= ~spefscr_ovh; \ |
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EV_SET_SPEFSCR(_sPefScR); \ |
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} while (0) |
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/* SPE floating point helpers. */ |
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#define EV_PMAX 0x7f7fffff |
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#define EV_NMAX 0xff7fffff |
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#define EV_PMIN 0x00800001 |
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#define EV_NMIN 0x80800001 |
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#define EV_IS_INFDENORMNAN(x) \ |
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(sim_fpu_is_infinity(x) || sim_fpu_is_denorm(x) || sim_fpu_is_nan(x)) |
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/* These aren't used (yet?) For now, SPU is always enabled.
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Would be nice if they were generated by igen for e500. */ |
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#define SPU_BEGIN \ |
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{ \ |
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if (MSR & msr_e500_spu_enable) { \ |
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#define SPU_END \ |
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} else { \ |
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/* FIXME: raise SPU unavailable. */ \ |
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} \ |
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} |
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/* These are also not yet used. */ |
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#define SPU_FP_BEGIN \ |
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{ |
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#define SPU_FP_END \ |
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{ \ |
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unsigned s = SPEFSCR; \ |
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/* Check SPEFSCR; raise exceptions if any required. */ \ |
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if (((spefscr_finxe || spefscr_finve) \ |
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&& (s & (spefscr_finvh|spefscr_finv))) \ |
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|| ((spefscr_finxe || spefscr_fdbze) \ |
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&& (s & (spefscr_fdbzh|spefscr_fdbz))) \ |
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|| ((spefscr_finxe || spefscr_funfe) \ |
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&& (s & (spefscr_funfh|spefscr_funf))) \ |
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|| ((spefscr_finxe || spefscr_fovfe) \ |
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&& (s & (spefscr_fovfh|spefscr_fovf)))) \ |
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/* FIXME: raise exceptions. */; \ |
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} \ |
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} |
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@ -0,0 +1,83 @@ |
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/* e500 registers, for PSIM, the PowerPC simulator.
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|
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Copyright 2003 Free Software Foundation, Inc. |
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|
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Contributed by Red Hat Inc; developed under contract from Motorola. |
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Written by matthew green <mrg@redhat.com>. |
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|
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This file is part of GDB. |
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|
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
|||
|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, |
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Boston, MA 02111-1307, USA. */ |
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/* e500 accumulator. */ |
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typedef unsigned64 accreg; |
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enum { |
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msr_e500_spu_enable = BIT(38) |
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}; |
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/* E500 regsiters. */ |
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enum |
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{ |
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spefscr_sovh = BIT(32), /* summary integer overlow (high) */ |
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spefscr_ovh = BIT(33), /* int overflow (high) */ |
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spefscr_fgh = BIT(34), /* FP guard (high) */ |
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spefscr_fxh = BIT(35), /* FP sticky (high) */ |
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spefscr_finvh = BIT(36), /* FP invalid operand (high) */ |
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spefscr_fdbzh = BIT(37), /* FP divide by zero (high) */ |
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spefscr_funfh = BIT(38), /* FP underflow (high) */ |
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spefscr_fovfh = BIT(39), /* FP overflow (high) */ |
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spefscr_finxs = BIT(42), /* FP inexact sticky */ |
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spefscr_finvs = BIT(43), /* FP invalid operand sticky */ |
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spefscr_fdbzs = BIT(44), /* FP divide by zero sticky */ |
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spefscr_funfs = BIT(45), /* FP underflow sticky */ |
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spefscr_fovfs = BIT(46), /* FP overflow sticky */ |
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spefscr_mode = BIT(47), /* SPU MODE (read only) */ |
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spefscr_sov = BIT(48), /* Summary integer overlow (low) */ |
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spefscr_ov = BIT(49), /* int overflow (low) */ |
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spefscr_fg = BIT(50), /* FP guard (low) */ |
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spefscr_fx = BIT(51), /* FP sticky (low) */ |
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spefscr_finv = BIT(52), /* FP invalid operand (low) */ |
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spefscr_fdbz = BIT(53), /* FP divide by zero (low) */ |
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spefscr_funf = BIT(54), /* FP underflow (low) */ |
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spefscr_fovf = BIT(55), /* FP overflow (low) */ |
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spefscr_finxe = BIT(57), /* FP inexact enable */ |
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spefscr_finve = BIT(58), /* FP invalid operand enable */ |
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spefscr_fdbze = BIT(59), /* FP divide by zero enable */ |
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spefscr_funfe = BIT(60), /* FP underflow enable */ |
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spefscr_fovfe = BIT(61), /* FP overflow enable */ |
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spefscr_frmc0 = BIT(62), /* FP round mode control */ |
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spefscr_frmc1 = BIT(63), |
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spefscr_frmc = (spefscr_frmc0 | spefscr_frmc1), |
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}; |
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struct e500_regs { |
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/* e500 high bits. */ |
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signed_word gprh[32]; |
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/* Accumulator */ |
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accreg acc; |
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}; |
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|
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/* SPE partially visible acculator */ |
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#define ACC cpu_registers(processor)->e500.acc |
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/* e500 register high bits */ |
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#define GPRH(N) cpu_registers(processor)->e500.gprh[N] |
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|
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/* e500 unified vector register */ |
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#define EVR(N) ((((unsigned64)GPRH(N)) << 32) | GPR(N)) |
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Reference in new issue