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gas/ 

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_assemble): Also zap movzx and movsx
	suffix for AT&T syntax.

gas/testsuite/

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.s: Add more tests for movsx and movzx.
	* gas/i386/x86_64.s: Likewise.

	* gas/i386/inval.s: Remove tests for movsxw and movzxw.

	* gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw,
	movsxl, movzxb and movzxw.

	* gas/i386/i386.d: Updated.
	* gas/i386/inval.l: Likewise.
	* gas/i386/x86_64.d: Likewise.
	* gas/i386/x86-64-inval.l: Likewise.

opcodes/

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.
insight_6_8-branch
H.J. Lu 19 years ago
parent
4ee521786f
commit
321fd21e2f
14 changed files with 238 additions and 114 deletions
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  1. 5
      gas/ChangeLog
  2. 33
      gas/config/tc-i386.c
  3. 15
      gas/testsuite/ChangeLog
  4. 19
      gas/testsuite/gas/i386/i386.d
  5. 19
      gas/testsuite/gas/i386/i386.s
  6. 63
      gas/testsuite/gas/i386/inval.l
  7. 3
      gas/testsuite/gas/i386/inval.s
  8. 76
      gas/testsuite/gas/i386/x86-64-inval.l
  9. 9
      gas/testsuite/gas/i386/x86-64-inval.s
  10. 33
      gas/testsuite/gas/i386/x86_64.d
  11. 33
      gas/testsuite/gas/i386/x86_64.s
  12. 5
      opcodes/ChangeLog
  13. 3
      opcodes/i386-opc.tbl
  14. 36
      opcodes/i386-tbl.h

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Also zap movzx and movsx
suffix for AT&T syntax.
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_reg_size): New.

33
gas/config/tc-i386.c
View File

@ -2277,25 +2277,20 @@ md_assemble (line)
if (!match_template ())
return;
if (intel_syntax)
{
/* Zap movzx and movsx suffix. The suffix may have been set from
"word ptr" or "byte ptr" on the source operand, but we'll use
the suffix later to choose the destination register. */
if ((i.tm.base_opcode & ~9) == 0x0fb6)
{
if (i.reg_operands < 2
&& !i.suffix
&& (!i.tm.opcode_modifier.no_bsuf
|| !i.tm.opcode_modifier.no_wsuf
|| !i.tm.opcode_modifier.no_lsuf
|| !i.tm.opcode_modifier.no_ssuf
|| !i.tm.opcode_modifier.no_ldsuf
|| !i.tm.opcode_modifier.no_qsuf))
as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
i.suffix = 0;
}
/* Zap movzx and movsx suffix. The suffix has been set from
"word ptr" or "byte ptr" on the source operand in Intel syntax
or extracted from mnemonic in AT&T syntax. But we'll use
the destination register to choose the suffix for encoding. */
if ((i.tm.base_opcode & ~9) == 0x0fb6)
{
/* In Intel syntax, there must be a suffix. In AT&T syntax, if
there is no suffix, the default will be byte extension. */
if (i.reg_operands != 2
&& !i.suffix
&& intel_syntax)
as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
i.suffix = 0;
}
if (i.tm.opcode_modifier.fwait)

15
gas/testsuite/ChangeLog
View File

@ -1,3 +1,18 @@
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.s: Add more tests for movsx and movzx.
* gas/i386/x86_64.s: Likewise.
* gas/i386/inval.s: Remove tests for movsxw and movzxw.
* gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw,
movsxl, movzxb and movzxw.
* gas/i386/i386.d: Updated.
* gas/i386/inval.l: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.s: Add tests for movsx, movzx and movnti.

19
gas/testsuite/gas/i386/i386.d
View File

@ -10,14 +10,25 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: df e0 fnstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
@ -29,9 +40,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: df e0 fnstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx

19
gas/testsuite/gas/i386/i386.s
View File

@ -6,15 +6,26 @@
fstsw
fstsw %ax
movsx %al, %si
movsx %al, %esi
movsx %ax, %esi
movsx (%eax), %edx
movsx (%eax), %dx
movsxb (%eax), %dx
movsxb (%eax), %edx
movsxw (%eax), %edx
movsbl (%eax), %edx
movsbw (%eax), %dx
movsbl (%eax), %edx
movswl (%eax), %edx
movzx %al, %si
movzx %al, %esi
movzx %ax, %esi
movzx (%eax), %edx
movzx (%eax), %dx
movzxb (%eax), %dx
movzxb (%eax), %edx
movzxw (%eax), %edx
movzb (%eax), %edx
movzb (%eax), %dx
movzbl (%eax), %edx
@ -30,10 +41,16 @@
fstsw
fstsw ax
movsx si,al
movsx esi,al
movsx esi,ax
movsx edx,BYTE PTR [eax]
movsx dx,BYTE PTR [eax]
movsx edx,WORD PTR [eax]
movzx si,al
movzx esi,al
movzx esi,ax
movzx edx,BYTE PTR [eax]
movzx dx,BYTE PTR [eax]
movzx edx,WORD PTR [eax]

63
gas/testsuite/gas/i386/inval.l
View File

@ -55,8 +55,9 @@
.*:56: Error: .*
.*:58: Error: .*
.*:59: Error: .*
.*:61: Error: .*
.*:62: Error: .*
.*:63: Error: .*
.*:64: Error: .*
.*:65: Error: .*
.*:66: Error: .*
.*:67: Error: .*
@ -70,14 +71,11 @@
.*:75: Error: .*
.*:76: Error: .*
.*:77: Error: .*
.*:78: Error: .*
.*:79: Error: .*
.*:80: Error: .*
.*:81: Error: .*
.*:82: Error: .*
.*:83: Error: .*
.*:84: Error: .*
.*:85: Error: .*
.*:87: Error: .*
GAS LISTING .*
@ -141,33 +139,30 @@ GAS LISTING .*
GAS LISTING .*
[ ]*58[ ]+movsxw \(%eax\),%eax
[ ]*59[ ]+movzxw \(%eax\),%eax
[ ]*58[ ]+movnti %ax, \(%eax\)
[ ]*59[ ]+movntiw %ax, \(%eax\)
[ ]*60[ ]+
[ ]*61[ ]+movnti %ax, \(%eax\)
[ ]*62[ ]+movntiw %ax, \(%eax\)
[ ]*63[ ]+
[ ]*64[ ]+\.intel_syntax noprefix
[ ]*65[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
[ ]*66[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
[ ]*67[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
[ ]*68[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
[ ]*69[ ]+movq xmm1, XMMWORD PTR \[esp\]
[ ]*70[ ]+movq xmm1, DWORD PTR \[esp\]
[ ]*71[ ]+movq xmm1, WORD PTR \[esp\]
[ ]*72[ ]+movq xmm1, BYTE PTR \[esp\]
[ ]*73[ ]+movq XMMWORD PTR \[esp\],xmm1
[ ]*74[ ]+movq DWORD PTR \[esp\],xmm1
[ ]*75[ ]+movq WORD PTR \[esp\],xmm1
[ ]*76[ ]+movq BYTE PTR \[esp\],xmm1
[ ]*77[ ]+fnstsw eax
[ ]*78[ ]+fnstsw al
[ ]*79[ ]+fstsw eax
[ ]*80[ ]+fstsw al
[ ]*81[ ]+
[ ]*82[ ]+movsx ax, \[eax\]
[ ]*83[ ]+movsx eax, \[eax\]
[ ]*84[ ]+movzx ax, \[eax\]
[ ]*85[ ]+movzx eax, \[eax\]
[ ]*86[ ]+
[ ]*87[ ]+movnti word ptr \[eax\], ax
[ ]*61[ ]+\.intel_syntax noprefix
[ ]*62[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
[ ]*63[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
[ ]*64[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
[ ]*65[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
[ ]*66[ ]+movq xmm1, XMMWORD PTR \[esp\]
[ ]*67[ ]+movq xmm1, DWORD PTR \[esp\]
[ ]*68[ ]+movq xmm1, WORD PTR \[esp\]
[ ]*69[ ]+movq xmm1, BYTE PTR \[esp\]
[ ]*70[ ]+movq XMMWORD PTR \[esp\],xmm1
[ ]*71[ ]+movq DWORD PTR \[esp\],xmm1
[ ]*72[ ]+movq WORD PTR \[esp\],xmm1
[ ]*73[ ]+movq BYTE PTR \[esp\],xmm1
[ ]*74[ ]+fnstsw eax
[ ]*75[ ]+fnstsw al
[ ]*76[ ]+fstsw eax
[ ]*77[ ]+fstsw al
[ ]*78[ ]+
[ ]*79[ ]+movsx ax, \[eax\]
[ ]*80[ ]+movsx eax, \[eax\]
[ ]*81[ ]+movzx ax, \[eax\]
[ ]*82[ ]+movzx eax, \[eax\]
[ ]*83[ ]+
[ ]*84[ ]+movnti word ptr \[eax\], ax

3
gas/testsuite/gas/i386/inval.s
View File

@ -55,9 +55,6 @@ foo: jaw foo
fstsw %eax
fstsw %al
movsxw (%eax),%eax
movzxw (%eax),%eax
movnti %ax, (%eax)
movntiw %ax, (%eax)

76
gas/testsuite/gas/i386/x86-64-inval.l
View File

@ -58,8 +58,6 @@
.*:59: Error: .*
.*:60: Error: .*
.*:61: Error: .*
.*:62: Error: .*
.*:63: Error: .*
.*:64: Error: .*
.*:65: Error: .*
.*:66: Error: .*
@ -67,6 +65,8 @@
.*:68: Error: .*
.*:69: Error: .*
.*:70: Error: .*
.*:71: Error: .*
.*:72: Error: .*
.*:73: Error: .*
.*:74: Error: .*
.*:75: Error: .*
@ -80,15 +80,6 @@
.*:83: Error: .*
.*:84: Error: .*
.*:85: Error: .*
.*:86: Error: .*
.*:87: Error: .*
.*:88: Error: .*
.*:89: Error: .*
.*:90: Error: .*
.*:91: Error: .*
.*:92: Error: .*
.*:93: Error: .*
.*:94: Error: .*
GAS LISTING .*
@ -153,39 +144,30 @@ GAS LISTING .*
[ ]*58[ ]+out %rax,\$8
[ ]*59[ ]+movsxb \(%rax\),%eax
[ ]*60[ ]+movsxb \(%rax\),%rax
[ ]*61[ ]+movsxw \(%rax\),%eax
[ ]*62[ ]+movsxw \(%rax\),%rax
[ ]*63[ ]+movsxl \(%rax\),%rax
[ ]*64[ ]+movzxb \(%rax\),%eax
[ ]*65[ ]+movzxb \(%rax\),%rax
[ ]*66[ ]+movzxw \(%rax\),%eax
[ ]*67[ ]+movzxw \(%rax\),%rax
[ ]*68[ ]+movzxl \(%rax\),%rax
[ ]*69[ ]+movnti %ax, \(%rax\)
[ ]*70[ ]+movntiw %ax, \(%rax\)
[ ]*71[ ]+
[ ]*72[ ]+\.intel_syntax noprefix
[ ]*73[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
[ ]*74[ ]+movq xmm1, XMMWORD PTR \[rsp\]
[ ]*75[ ]+movq xmm1, DWORD PTR \[rsp\]
[ ]*76[ ]+movq xmm1, WORD PTR \[rsp\]
[ ]*77[ ]+movq xmm1, BYTE PTR \[rsp\]
[ ]*78[ ]+movq XMMWORD PTR \[rsp\],xmm1
[ ]*79[ ]+movq DWORD PTR \[rsp\],xmm1
[ ]*80[ ]+movq WORD PTR \[rsp\],xmm1
[ ]*81[ ]+movq BYTE PTR \[rsp\],xmm1
[ ]*82[ ]+fnstsw eax
[ ]*83[ ]+fnstsw al
[ ]*84[ ]+fstsw eax
[ ]*85[ ]+fstsw al
[ ]*86[ ]+in rax,8
[ ]*87[ ]+out 8,rax
[ ]*88[ ]+movsx ax, \[rax\]
[ ]*89[ ]+movsx eax, \[rax\]
[ ]*90[ ]+movsx rax, \[rax\]
[ ]*91[ ]+movzx ax, \[rax\]
[ ]*92[ ]+movzx eax, \[rax\]
[ ]*93[ ]+movzx rax, \[rax\]
[ ]*94[ ]+movnti word ptr \[rax\], ax
[ ]*59[ ]+movzxl \(%rax\),%rax
[ ]*60[ ]+movnti %ax, \(%rax\)
[ ]*61[ ]+movntiw %ax, \(%rax\)
[ ]*62[ ]+
[ ]*63[ ]+\.intel_syntax noprefix
[ ]*64[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
[ ]*65[ ]+movq xmm1, XMMWORD PTR \[rsp\]
[ ]*66[ ]+movq xmm1, DWORD PTR \[rsp\]
[ ]*67[ ]+movq xmm1, WORD PTR \[rsp\]
[ ]*68[ ]+movq xmm1, BYTE PTR \[rsp\]
[ ]*69[ ]+movq XMMWORD PTR \[rsp\],xmm1
[ ]*70[ ]+movq DWORD PTR \[rsp\],xmm1
[ ]*71[ ]+movq WORD PTR \[rsp\],xmm1
[ ]*72[ ]+movq BYTE PTR \[rsp\],xmm1
[ ]*73[ ]+fnstsw eax
[ ]*74[ ]+fnstsw al
[ ]*75[ ]+fstsw eax
[ ]*76[ ]+fstsw al
[ ]*77[ ]+in rax,8
[ ]*78[ ]+out 8,rax
[ ]*79[ ]+movsx ax, \[rax\]
[ ]*80[ ]+movsx eax, \[rax\]
[ ]*81[ ]+movsx rax, \[rax\]
[ ]*82[ ]+movzx ax, \[rax\]
[ ]*83[ ]+movzx eax, \[rax\]
[ ]*84[ ]+movzx rax, \[rax\]
[ ]*85[ ]+movnti word ptr \[rax\], ax

9
gas/testsuite/gas/i386/x86-64-inval.s
View File

@ -56,15 +56,6 @@ foo: jcxz foo # No prefix exists to select CX as a counter
fstsw %al
in $8,%rax
out %rax,$8
movsxb (%rax),%eax
movsxb (%rax),%rax
movsxw (%rax),%eax
movsxw (%rax),%rax
movsxl (%rax),%rax
movzxb (%rax),%eax
movzxb (%rax),%rax
movzxw (%rax),%eax
movzxw (%rax),%rax
movzxl (%rax),%rax
movnti %ax, (%rax)
movntiw %ax, (%rax)

33
gas/testsuite/gas/i386/x86_64.d
View File

@ -158,6 +158,12 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 89 04 25 11 22 33 ff mov %rax,0xffffffffff332211
[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
@ -166,6 +172,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
@ -177,11 +188,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
@ -202,10 +224,21 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)

33
gas/testsuite/gas/i386/x86_64.s
View File

@ -194,6 +194,12 @@ cmpxchg16b (%rax)
cmpxchg16b oword ptr [rax]
.att_syntax
movsx %al, %si
movsx %al, %esi
movsx %al, %rsi
movsx %ax, %esi
movsx %ax, %rsi
movsx %eax, %rsi
movsx (%rax), %edx
movsx (%rax), %rdx
movsx (%rax), %dx
@ -203,6 +209,11 @@ cmpxchg16b oword ptr [rax]
movswl (%rax), %edx
movswq (%rax), %rdx
movzx %al, %si
movzx %al, %esi
movzx %al, %rsi
movzx %ax, %esi
movzx %ax, %rsi
movzx (%rax), %edx
movzx (%rax), %rdx
movzx (%rax), %dx
@ -216,12 +227,23 @@ cmpxchg16b oword ptr [rax]
movzwq (%rax), %rdx
.intel_syntax noprefix
movsx si,al
movsx esi,al
movsx rsi,al
movsx esi,ax
movsx rsi,ax
movsx rsi,eax
movsx edx,BYTE PTR [rax]
movsx rdx,BYTE PTR [rax]
movsx dx,BYTE PTR [rax]
movsx edx,WORD PTR [rax]
movsx rdx,WORD PTR [rax]
movzx si,al
movzx esi,al
movzx rsi,al
movzx esi,ax
movzx rsi,ax
movzx edx,BYTE PTR [rax]
movzx rdx,BYTE PTR [rax]
movzx dx,BYTE PTR [rax]
@ -249,10 +271,21 @@ cmpxchg16b oword ptr [rax]
movsx (%rax),%ax
movsx (%rax),%eax
movsx (%rax),%rax
movsxb (%rax), %dx
movsxb (%rax), %edx
movsxb (%rax), %rdx
movsxw (%rax), %edx
movsxw (%rax), %rdx
movsxl (%rax), %rdx
movsxd (%rax),%rax
movzx (%rax),%ax
movzx (%rax),%eax
movzx (%rax),%rax
movzxb (%rax), %dx
movzxb (%rax), %edx
movzxb (%rax), %rdx
movzxw (%rax), %edx
movzxw (%rax), %rdx
movnti %eax, (%rax)
movntil %eax, (%rax)

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
* i386-tbl.h: Regenerated.
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (Mx): New.

3
opcodes/i386-opc.tbl
View File

@ -64,6 +64,8 @@ movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
// Intel Syntax next 3 insns
movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
@ -84,6 +86,7 @@ movzwq, 2, 0xfb7, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
// Intel Syntax next 2 insns (the 64-bit variants are not particulary
// useful since the zero extend 32->64 is implicit, but we can encode them).
movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }

36
opcodes/i386-tbl.h
View File

@ -358,6 +358,30 @@ const template i386_optab[] =
{ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "movsx", 2, 0xfbf, None, 2,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0 },
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0 } },
{ { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "movsx", 2, 0x63, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1,
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
1, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0 } },
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "movsx", 2, 0xfbe, None, 2,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@ -490,6 +514,18 @@ const template i386_optab[] =
{ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "movzx", 2, 0xfb7, None, 2,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0 },
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0 } },
{ { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "movzx", 2, 0xfb6, None, 2,
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },

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