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@ -223,19 +223,9 @@ const struct powerpc_operand powerpc_operands[] = |
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#define D CT + 1 |
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{ 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
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/* The DE field in a DE form instruction. This is like D, but is 12
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bits only. */ |
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#define DE D + 1 |
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{ 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
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/* The DES field in a DES form instruction. This is like DS, but is 14
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bits only (12 stored.) */ |
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#define DES DE + 1 |
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{ 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
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/* The DQ field in a DQ form instruction. This is like D, but the
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lower four bits are forced to zero. */ |
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#define DQ DES + 1 |
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#define DQ D + 1 |
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{ 0xfff0, 0, NULL, NULL, |
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PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, |
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@ -1487,10 +1477,6 @@ extract_xb6s (unsigned long insn, |
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#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
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#define DS_MASK DSO (0x3f, 3) |
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/* A DE form instruction. */ |
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#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) |
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#define DE_MASK DEO (0x3e, 0xf) |
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/* An EVSEL form instruction. */ |
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#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) |
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#define EVSEL_MASK EVSEL(0x3f, 0xff) |
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@ -1841,7 +1827,6 @@ extract_xb6s (unsigned long insn, |
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#define MFDEC1 PPC_OPCODE_POWER |
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#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE |
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#define BOOKE PPC_OPCODE_BOOKE |
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#define BOOKE64 PPC_OPCODE_BOOKE64 |
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#define CLASSIC PPC_OPCODE_CLASSIC |
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#define PPCE300 PPC_OPCODE_E300 |
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#define PPCSPE PPC_OPCODE_SPE |
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@ -1850,7 +1835,6 @@ extract_xb6s (unsigned long insn, |
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#define PPCBRLK PPC_OPCODE_BRLOCK |
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#define PPCPMR PPC_OPCODE_PMR |
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#define PPCCHLK PPC_OPCODE_CACHELCK |
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#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 |
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#define PPCRFMCI PPC_OPCODE_RFMCI |
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#define E500MC PPC_OPCODE_E500MC |
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@ -2525,11 +2509,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}}, |
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{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}}, |
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{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}}, |
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{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}}, |
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{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}}, |
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{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}}, |
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{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}}, |
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{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}}, |
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@ -3070,9 +3049,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, |
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{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}}, |
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{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}}, |
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{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}}, |
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{"rfid", XL(19,18), 0xffffffff, PPC64, {0}}, |
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{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}}, |
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@ -3272,9 +3248,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, |
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{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}}, |
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{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}}, |
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{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}}, |
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{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, |
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{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, |
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@ -3291,11 +3264,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, |
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{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}}, |
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{"be", B(22,0,0), B_MASK, BOOKE64, {LI}}, |
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{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}}, |
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{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}}, |
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{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}}, |
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{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}}, |
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{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}}, |
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{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, |
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@ -3441,10 +3410,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}}, |
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{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}}, |
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{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}}, |
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{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}}, |
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{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, |
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@ -3482,12 +3447,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}}, |
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{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}}, |
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{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"wait", X(31,62), 0xffffffff, E500MC, {0}}, |
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{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}}, |
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{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}}, |
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{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}}, |
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@ -3527,9 +3488,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}}, |
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{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}}, |
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{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}}, |
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@ -3554,10 +3512,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}}, |
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{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}}, |
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{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}}, |
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{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}}, |
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{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}}, |
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@ -3577,7 +3531,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, |
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{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, |
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{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}}, |
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{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}}, |
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{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}}, |
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@ -3602,9 +3556,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}}, |
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{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}}, |
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{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}}, |
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@ -3614,7 +3565,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}}, |
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{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}}, |
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{"dcbtlse", X(31,174), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}}, |
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@ -3628,8 +3579,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}}, |
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{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}}, |
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{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}}, |
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{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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@ -3657,7 +3606,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}}, |
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{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}}, |
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{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}}, |
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{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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@ -3684,7 +3632,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, |
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{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}}, |
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{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}}, |
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{"icblce", X(31,238), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}}, |
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{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}}, |
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@ -3695,10 +3643,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}}, |
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{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}}, |
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{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}}, |
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{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}}, |
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{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}}, |
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{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}}, |
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@ -3730,9 +3674,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}}, |
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{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}}, |
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{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}}, |
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{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}}, |
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{"mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}}, |
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@ -3747,8 +3688,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}}, |
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{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}}, |
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{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}}, |
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{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}}, |
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{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}}, |
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@ -3984,8 +3923,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}}, |
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{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}}, |
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{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}}, |
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@ -4006,18 +3943,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}}, |
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{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}}, |
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{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}}, |
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{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, |
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{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, |
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{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}}, |
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{"dcblce", X(31,398), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}}, |
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@ -4026,7 +3957,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}}, |
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{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}}, |
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{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}}, |
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{"mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}}, |
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@ -4044,8 +3974,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}}, |
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{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}}, |
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{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}}, |
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{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}}, |
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{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}}, |
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{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}}, |
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@ -4084,13 +4012,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}}, |
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{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}}, |
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{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}}, |
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@ -4255,8 +4179,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}}, |
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{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}}, |
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{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}}, |
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{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}}, |
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@ -4266,18 +4188,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}}, |
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{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}}, |
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{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}}, |
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{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}}, |
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{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}}, |
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{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}}, |
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{"icbtlse", X(31,494), X_MASK, PPCCHLK, {CT, RA, RB}}, |
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{"slbia", X(31,498), 0xffffffff, PPC64, {0}}, |
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@ -4285,8 +4204,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}}, |
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{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}}, |
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{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}}, |
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{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}}, |
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@ -4334,12 +4251,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}}, |
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{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}}, |
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{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}}, |
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{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}}, |
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{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}}, |
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{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}}, |
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@ -4356,8 +4267,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}}, |
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{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}}, |
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{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}}, |
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{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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@ -4375,7 +4284,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}}, |
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{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}}, |
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{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}}, |
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{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}}, |
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@ -4395,8 +4303,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}}, |
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{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}}, |
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{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}}, |
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{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}}, |
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@ -4430,10 +4336,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}}, |
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{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}}, |
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{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}}, |
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{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}}, |
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{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}}, |
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@ -4444,8 +4346,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}}, |
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{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}}, |
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{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}}, |
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{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}}, |
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{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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@ -4471,7 +4371,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}}, |
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{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}}, |
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{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}}, |
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{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}}, |
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{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}}, |
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@ -4505,10 +4404,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}}, |
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{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}}, |
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{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}}, |
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{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}}, |
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{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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@ -4521,7 +4416,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, |
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{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}}, |
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{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}}, |
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{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}}, |
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{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}}, |
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@ -4542,10 +4436,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}}, |
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{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}}, |
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{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}}, |
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{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}}, |
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@ -4568,7 +4458,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}}, |
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{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}}, |
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{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}}, |
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{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}}, |
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@ -4594,15 +4483,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}}, |
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{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}}, |
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{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, |
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{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, |
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{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, |
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{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, |
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{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}}, |
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{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}}, |
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{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}}, |
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{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}}, |
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@ -4623,10 +4506,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}}, |
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{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}}, |
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{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}}, |
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{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}}, |
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{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}}, |
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@ -4645,17 +4524,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}}, |
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{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}}, |
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{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}}, |
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{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}}, |
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{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}}, |
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{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}}, |
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@ -4672,25 +4545,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}}, |
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{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}}, |
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{"extsw", XRC(31,986,0), XRB_MASK, PPC64, {RA, RS}}, |
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{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}}, |
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{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}}, |
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{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}}, |
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{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}}, |
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{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}}, |
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{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}}, |
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{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}}, |
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{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}}, |
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{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}}, |
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{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}}, |
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@ -4703,7 +4570,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, |
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{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, |
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{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}}, |
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{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}}, |
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{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}}, |
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@ -4788,21 +4654,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}}, |
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{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}}, |
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{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}}, |
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{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}}, |
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{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}}, |
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{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}}, |
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{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}}, |
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{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}}, |
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{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}}, |
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{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}}, |
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{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}}, |
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{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}}, |
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{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}}, |
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{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}}, |
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{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}}, |
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{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}}, |
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{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}}, |
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{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}}, |
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@ -4920,19 +4771,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}}, |
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{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}}, |
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{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}}, |
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{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}}, |
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{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}}, |
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{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}}, |
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{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}}, |
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{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}}, |
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{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}}, |
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{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}}, |
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{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}}, |
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{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}}, |
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{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}}, |
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{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}}, |
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{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}}, |
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{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}}, |
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Ben Elliston
18 years ago