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Add generated source files and fix thinko in aarch64-asm.c

binutils-2_42-branch
Nick Clifton 2 years ago
parent
b33f1bcd15
commit
2db11bdf84
4 changed files with 1058 additions and 566 deletions
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  1. 136
      opcodes/aarch64-asm-2.c
  2. 2
      opcodes/aarch64-asm.c
  3. 1473
      opcodes/aarch64-dis-2.c
  4. 13
      opcodes/aarch64-opc-2.c

136
opcodes/aarch64-asm-2.c
View File

@ -670,26 +670,26 @@ aarch64_insert_operand (const aarch64_operand *self,
case 204:
case 205:
case 206:
case 207:
case 208:
case 209:
case 210:
case 211:
case 215:
case 216:
case 217:
case 218:
case 221:
case 225:
case 232:
case 233:
case 240:
case 241:
case 219:
case 227:
case 231:
case 235:
case 242:
case 243:
case 250:
case 251:
case 252:
case 253:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 113:
case 114:
case 275:
case 277:
case 285:
case 287:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -701,7 +701,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 35:
case 36:
case 37:
case 279:
case 289:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 38:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -747,13 +747,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 200:
case 201:
case 202:
case 246:
case 273:
case 274:
case 276:
case 278:
case 256:
case 283:
case 284:
case 286:
case 288:
case 293:
case 294:
return aarch64_ins_imm (self, info, code, inst, errors);
case 46:
case 47:
@ -901,74 +901,90 @@ aarch64_insert_operand (const aarch64_operand *self,
case 192:
case 193:
case 194:
case 259:
case 269:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 207:
case 208:
case 209:
case 210:
return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 211:
case 212:
case 213:
case 214:
case 215:
case 216:
case 217:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 219:
return aarch64_ins_sve_index (self, info, code, inst, errors);
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
case 220:
case 221:
case 222:
case 239:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 223:
case 224:
case 225:
case 226:
case 227:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 228:
return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
case 229:
case 238:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 230:
case 231:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 232:
case 249:
case 295:
case 296:
case 297:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 233:
case 234:
case 236:
case 247:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 235:
case 237:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 238:
case 239:
case 248:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 240:
case 241:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 244:
case 246:
case 257:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 245:
case 247:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 254:
case 255:
case 270:
case 271:
case 272:
case 273:
case 274:
case 275:
case 276:
case 277:
case 278:
case 279:
case 280:
case 281:
case 282:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 258:
case 259:
case 260:
case 261:
case 262:
case 263:
case 264:
case 265:
case 266:
case 267:
case 268:
case 269:
case 270:
case 271:
case 272:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 248:
case 249:
case 250:
case 251:
case 252:
case 253:
case 254:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 255:
case 265:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 256:
case 266:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 257:
case 267:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 258:
case 268:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 280:
case 281:
case 282:
case 290:
case 291:
case 292:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}

2
opcodes/aarch64-asm.c
View File

@ -1999,7 +1999,7 @@ do_special_encoding (struct aarch64_inst *inst)
if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs)
{
enum aarch64_opnd_qualifier qualifier[1];
enum aarch64_opnd_qualifier qualifier[2];
aarch64_insn value1 = 0;
idx = 0;
qualifier[0] = inst->operands[idx].qualifier;

1473
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large

13
opcodes/aarch64-opc-2.c
View File

@ -231,6 +231,14 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off3}, "ZA0 tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_1,FLD_off2}, "1 bit ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_2,FLD_ol}, "2 ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3}, "3 ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off2}, "ZA0 tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn,FLD_ol}, "1 bit ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off2}, "2 bit ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3}, "3 bit ZA tile"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
@ -241,8 +249,10 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz}, "a 5 bit idexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
@ -309,6 +319,9 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 2 SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 3 SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 4 SVE vector registers"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
};

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