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aarch64: Add the SME2 FP<->int conversion instructions 

This patch adds the SME2 versions of the FP<->integer conversion
instructions FCVT* and *CVTF.  It also adds FP rounding instructions
FRINT*, which share the same format.
users/aburgess/try-core-file-pid0
Richard Sandiford 3 years ago
parent
5f05951e4b
commit
28ef4f20c0
9 changed files with 1191 additions and 750 deletions
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  1. 3
      gas/testsuite/gas/aarch64/sme2-23-invalid.d
  2. 14
      gas/testsuite/gas/aarch64/sme2-23-invalid.l
  3. 8
      gas/testsuite/gas/aarch64/sme2-23-invalid.s
  4. 3
      gas/testsuite/gas/aarch64/sme2-23-noarch.d
  5. 65
      gas/testsuite/gas/aarch64/sme2-23-noarch.l
  6. 73
      gas/testsuite/gas/aarch64/sme2-23.d
  7. 79
      gas/testsuite/gas/aarch64/sme2-23.s
  8. 1676
      opcodes/aarch64-dis-2.c
  9. 20
      opcodes/aarch64-tbl.h

3
gas/testsuite/gas/aarch64/sme2-23-invalid.d
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@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: sme2-23-invalid.s
#error_output: sme2-23-invalid.l

14
gas/testsuite/gas/aarch64/sme2-23-invalid.l
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@ -0,0 +1,14 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `fcvtzs 0,{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fcvtzs {z0\.s,z1\.s},0'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtzs {z0\.s,z1\.s},{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtzs {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtzs {z30\.h,z31\.h},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtzs {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtzs {z0\.d,z1\.d},{z30\.d-z31\.d}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtzs {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `fcvtzs {z1\.s,z2\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fcvtzs {z0\.s,z1\.s},{z29\.s-z30\.s}'

8
gas/testsuite/gas/aarch64/sme2-23-invalid.s
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@ -0,0 +1,8 @@
fcvtzs 0, { z0.s - z1.s }
fcvtzs { z0.s, z1.s }, 0
fcvtzs { z0.s, z1.s }, { z0.h - z1.h }
fcvtzs { z30.h, z31.h }, { z0.s - z1.s }
fcvtzs { z0.d, z1.d }, { z30.d - z31.d }
fcvtzs { z1.s, z2.s }, { z30.s - z31.s }
fcvtzs { z0.s, z1.s }, { z29.s - z30.s }

3
gas/testsuite/gas/aarch64/sme2-23-noarch.d
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@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sme2-23.s
#error_output: sme2-23-noarch.l

65
gas/testsuite/gas/aarch64/sme2-23-noarch.l
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@ -0,0 +1,65 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzs {z24\.s-z27\.s},{z8\.s-z11\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z12\.s,z13\.s},{z14\.s-z15\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtzu {z16\.s-z19\.s},{z12\.s-z15\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frinta {z24\.s-z27\.s},{z8\.s-z11\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintm {z24\.s-z27\.s},{z8\.s-z11\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintn {z24\.s-z27\.s},{z8\.s-z11\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `frintp {z24\.s-z27\.s},{z8\.s-z11\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `scvtf {z24\.s-z27\.s},{z8\.s-z11\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s,z1\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z30\.s,z31\.s},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s,z1\.s},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z10\.s,z11\.s},{z26\.s-z27\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z28\.s-z31\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z0\.s-z3\.s},{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `ucvtf {z24\.s-z27\.s},{z8\.s-z11\.s}'

73
gas/testsuite/gas/aarch64/sme2-23.d
View File

@ -0,0 +1,73 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: c121e000 fcvtzs {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c121e01e fcvtzs {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c121e3c0 fcvtzs {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c121e34a fcvtzs {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c131e000 fcvtzs {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c131e01c fcvtzs {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c131e380 fcvtzs {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c131e118 fcvtzs {z24\.s-z27\.s}, {z8\.s-z11\.s}
[^:]+: c121e020 fcvtzu {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c121e03e fcvtzu {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c121e3e0 fcvtzu {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c121e1ec fcvtzu {z12\.s-z13\.s}, {z14\.s-z15\.s}
[^:]+: c131e020 fcvtzu {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c131e03c fcvtzu {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c131e3a0 fcvtzu {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c131e1b0 fcvtzu {z16\.s-z19\.s}, {z12\.s-z15\.s}
[^:]+: c1ace000 frinta {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c1ace01e frinta {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c1ace3c0 frinta {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c1ace34a frinta {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c1bce000 frinta {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c1bce01c frinta {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c1bce380 frinta {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c1bce118 frinta {z24\.s-z27\.s}, {z8\.s-z11\.s}
[^:]+: c1aae000 frintm {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c1aae01e frintm {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c1aae3c0 frintm {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c1aae34a frintm {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c1bae000 frintm {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c1bae01c frintm {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c1bae380 frintm {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c1bae118 frintm {z24\.s-z27\.s}, {z8\.s-z11\.s}
[^:]+: c1a8e000 frintn {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c1a8e01e frintn {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c1a8e3c0 frintn {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c1a8e34a frintn {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c1b8e000 frintn {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c1b8e01c frintn {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c1b8e380 frintn {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c1b8e118 frintn {z24\.s-z27\.s}, {z8\.s-z11\.s}
[^:]+: c1a9e000 frintp {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c1a9e01e frintp {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c1a9e3c0 frintp {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c1a9e34a frintp {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c1b9e000 frintp {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c1b9e01c frintp {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c1b9e380 frintp {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c1b9e118 frintp {z24\.s-z27\.s}, {z8\.s-z11\.s}
[^:]+: c122e000 scvtf {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c122e01e scvtf {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c122e3c0 scvtf {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c122e34a scvtf {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c132e000 scvtf {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c132e01c scvtf {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c132e380 scvtf {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c132e118 scvtf {z24\.s-z27\.s}, {z8\.s-z11\.s}
[^:]+: c122e020 ucvtf {z0\.s-z1\.s}, {z0\.s-z1\.s}
[^:]+: c122e03e ucvtf {z30\.s-z31\.s}, {z0\.s-z1\.s}
[^:]+: c122e3e0 ucvtf {z0\.s-z1\.s}, {z30\.s-z31\.s}
[^:]+: c122e36a ucvtf {z10\.s-z11\.s}, {z26\.s-z27\.s}
[^:]+: c132e020 ucvtf {z0\.s-z3\.s}, {z0\.s-z3\.s}
[^:]+: c132e03c ucvtf {z28\.s-z31\.s}, {z0\.s-z3\.s}
[^:]+: c132e3a0 ucvtf {z0\.s-z3\.s}, {z28\.s-z31\.s}
[^:]+: c132e138 ucvtf {z24\.s-z27\.s}, {z8\.s-z11\.s}

79
gas/testsuite/gas/aarch64/sme2-23.s
View File

@ -0,0 +1,79 @@
fcvtzs { z0.s, z1.s }, { z0.s - z1.s }
fcvtzs { z30.s, z31.s }, { z0.s - z1.s }
fcvtzs { z0.s, z1.s }, { z30.s - z31.s }
fcvtzs { z10.s, z11.s }, { z26.s - z27.s }
fcvtzs { z0.s - z3.s }, { z0.s - z3.s }
fcvtzs { z28.s - z31.s }, { z0.s - z3.s }
fcvtzs { z0.s - z3.s }, { z28.s - z31.s }
fcvtzs { z24.s - z27.s }, { z8.s - z11.s }
fcvtzu { z0.s, z1.s }, { z0.s - z1.s }
fcvtzu { z30.s, z31.s }, { z0.s - z1.s }
fcvtzu { z0.s, z1.s }, { z30.s - z31.s }
fcvtzu { z12.s, z13.s }, { z14.s - z15.s }
fcvtzu { z0.s - z3.s }, { z0.s - z3.s }
fcvtzu { z28.s - z31.s }, { z0.s - z3.s }
fcvtzu { z0.s - z3.s }, { z28.s - z31.s }
fcvtzu { z16.s - z19.s }, { z12.s - z15.s }
frinta { z0.s, z1.s }, { z0.s - z1.s }
frinta { z30.s, z31.s }, { z0.s - z1.s }
frinta { z0.s, z1.s }, { z30.s - z31.s }
frinta { z10.s, z11.s }, { z26.s - z27.s }
frinta { z0.s - z3.s }, { z0.s - z3.s }
frinta { z28.s - z31.s }, { z0.s - z3.s }
frinta { z0.s - z3.s }, { z28.s - z31.s }
frinta { z24.s - z27.s }, { z8.s - z11.s }
frintm { z0.s, z1.s }, { z0.s - z1.s }
frintm { z30.s, z31.s }, { z0.s - z1.s }
frintm { z0.s, z1.s }, { z30.s - z31.s }
frintm { z10.s, z11.s }, { z26.s - z27.s }
frintm { z0.s - z3.s }, { z0.s - z3.s }
frintm { z28.s - z31.s }, { z0.s - z3.s }
frintm { z0.s - z3.s }, { z28.s - z31.s }
frintm { z24.s - z27.s }, { z8.s - z11.s }
frintn { z0.s, z1.s }, { z0.s - z1.s }
frintn { z30.s, z31.s }, { z0.s - z1.s }
frintn { z0.s, z1.s }, { z30.s - z31.s }
frintn { z10.s, z11.s }, { z26.s - z27.s }
frintn { z0.s - z3.s }, { z0.s - z3.s }
frintn { z28.s - z31.s }, { z0.s - z3.s }
frintn { z0.s - z3.s }, { z28.s - z31.s }
frintn { z24.s - z27.s }, { z8.s - z11.s }
frintp { z0.s, z1.s }, { z0.s - z1.s }
frintp { z30.s, z31.s }, { z0.s - z1.s }
frintp { z0.s, z1.s }, { z30.s - z31.s }
frintp { z10.s, z11.s }, { z26.s - z27.s }
frintp { z0.s - z3.s }, { z0.s - z3.s }
frintp { z28.s - z31.s }, { z0.s - z3.s }
frintp { z0.s - z3.s }, { z28.s - z31.s }
frintp { z24.s - z27.s }, { z8.s - z11.s }
scvtf { z0.s, z1.s }, { z0.s - z1.s }
scvtf { z30.s, z31.s }, { z0.s - z1.s }
scvtf { z0.s, z1.s }, { z30.s - z31.s }
scvtf { z10.s, z11.s }, { z26.s - z27.s }
scvtf { z0.s - z3.s }, { z0.s - z3.s }
scvtf { z28.s - z31.s }, { z0.s - z3.s }
scvtf { z0.s - z3.s }, { z28.s - z31.s }
scvtf { z24.s - z27.s }, { z8.s - z11.s }
ucvtf { z0.s, z1.s }, { z0.s - z1.s }
ucvtf { z30.s, z31.s }, { z0.s - z1.s }
ucvtf { z0.s, z1.s }, { z30.s - z31.s }
ucvtf { z10.s, z11.s }, { z26.s - z27.s }
ucvtf { z0.s - z3.s }, { z0.s - z3.s }
ucvtf { z28.s - z31.s }, { z0.s - z3.s }
ucvtf { z0.s - z3.s }, { z28.s - z31.s }
ucvtf { z24.s - z27.s }, { z8.s - z11.s }

1676
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large

20
opcodes/aarch64-tbl.h
View File

@ -1711,6 +1711,10 @@
{ \
QLF3(S_S,P_M,S_S), \
}
#define OP_SVE_SS \
{ \
QLF2(S_S,S_S), \
}
#define OP_SVE_SU \
{ \
QLF2(S_S,NIL), \
@ -5379,6 +5383,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("fclamp", 0xc120c000, 0xff20fc01, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
SME2_INSN ("fclamp", 0xc120c800, 0xff20fc03, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
SME2_INSN ("fcvtzs", 0xc121e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("fcvtzs", 0xc131e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("fcvtzu", 0xc121e020, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("fcvtzu", 0xc131e020, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("fdot", 0xc1501008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("fdot", 0xc1509008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("fdot", 0xc1201000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
@ -5429,6 +5437,14 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("fmlsl", 0xc1300808, 0xfff09c1c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("fmlsl", 0xc1a00808, 0xffe19c3c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("fmlsl", 0xc1a10808, 0xffe39c7c, sme_misc, 0, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("frinta", 0xc1ace000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("frinta", 0xc1bce000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("frintm", 0xc1aae000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("frintm", 0xc1bae000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("frintn", 0xc1a8e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("frintn", 0xc1b8e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("frintp", 0xc1a9e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("frintp", 0xc1b9e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("fvdot", 0xc1500008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
@ -5526,6 +5542,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
SME2_INSN ("sclamp", 0xc120c400, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("sclamp", 0xc120cc00, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("scvtf", 0xc122e000, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("scvtf", 0xc132e000, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("sdot", 0xc1501000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("sdot", 0xc1509000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("sdot", 0xc1601408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),
@ -5675,6 +5693,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("svdot", 0xc1508020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("uclamp", 0xc120c401, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("uclamp", 0xc120cc01, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SME2_INSN ("ucvtf", 0xc122e020, 0xfffffc21, sve_misc, 0, OP2 (SME_Zdnx2, SME_Znx2), OP_SVE_SS, 0, 0),
SME2_INSN ("ucvtf", 0xc132e020, 0xfffffc63, sve_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_SS, 0, 0),
SME2_INSN ("udot", 0xc1501010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("udot", 0xc1509010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0),
SME2_INSN ("udot", 0xc1601418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0),

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