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PowerPC table driven -Mraw disassembly 

opcodes/
	* ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
	Don't special case PPC_OPCODE_RAW.
	(lookup_prefix): Likewise.
	(lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
	(print_insn_powerpc): ..update caller.
	* ppc-opc.c (EXT): Define.
	(powerpc_opcodes): Mark extended mnemonics with EXT.
	(prefix_opcodes, vle_opcodes): Likewise.
	(XISEL, XISEL_MASK): Add cr field and simplify.
	(powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
	all isel variants to where the base mnemonic belongs.  Sort dstt,
	dststt and dssall.
gas/
	* testsuite/gas/ppc/raw.s,
	* testsuite/gas/ppc/raw.d: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
binutils-2_37-branch
Alan Modra 5 years ago
parent
d6249f5f1c
commit
1ff6a3b8e5
7 changed files with 1755 additions and 1635 deletions
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  1. 6
      gas/ChangeLog
  2. 1
      gas/testsuite/gas/ppc/ppc.exp
  3. 62
      gas/testsuite/gas/ppc/raw.d
  4. 52
      gas/testsuite/gas/ppc/raw.s
  5. 15
      opcodes/ChangeLog
  6. 48
      opcodes/ppc-dis.c
  7. 3206
      opcodes/ppc-opc.c

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2021-05-29 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/raw.s,
* testsuite/gas/ppc/raw.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/c0.d: New test.

1
gas/testsuite/gas/ppc/ppc.exp
View File

@ -151,3 +151,4 @@ run_dump_test "rop-checks"
run_dump_test "dcbt"
run_dump_test "pr27676"
run_dump_test "raw"

62
gas/testsuite/gas/ppc/raw.d
View File

@ -0,0 +1,62 @@
#as: -mpower10
#objdump: -d -Mpower10 -Mraw
#name: raw disassembly
.*: file format .*
Disassembly of section \.text:
0+ <\.text>:
0: (f0 64 24 90|90 24 64 f0) xxlor vs3,vs4,vs4
4: (f0 64 25 10|10 25 64 f0) xxlnor vs3,vs4,vs4
8: (f0 64 26 80|80 26 64 f0) xvcpsgnsp vs3,vs4,vs4
c: (10 64 24 84|84 24 64 10) vor v3,v4,v4
10: (7c 83 23 78|78 23 83 7c) or r3,r4,r4
14: (7c 83 20 f8|f8 20 83 7c) nor r3,r4,r4
18: (4c a6 30 42|42 30 a6 4c) crnor 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+eq
1c: (4c e7 39 82|82 39 e7 4c) crxor 4\*cr1\+so,4\*cr1\+so,4\*cr1\+so
20: (4c 00 02 42|42 02 00 4c) creqv lt,lt,lt
24: (4c 22 13 82|82 13 22 4c) cror gt,eq,eq
28: (f0 64 20 50|50 20 64 f0) xxpermdi vs3,vs4,vs4,0
2c: (f0 64 23 50|50 23 64 f0) xxpermdi vs3,vs4,vs4,3
30: (f0 64 28 50|50 28 64 f0) xxpermdi vs3,vs4,vs5,0
34: (f0 64 2b 50|50 2b 64 f0) xxpermdi vs3,vs4,vs5,3
38: (f0 64 22 50|50 22 64 f0) xxpermdi vs3,vs4,vs4,2
3c: (10 60 23 ca|ca 23 60 10) vctsxs v3,v4,0
40: (38 60 00 7b|7b 00 60 38) addi r3,0,123
44: (3c 80 01 c8|c8 01 80 3c) addis r4,0,456
48: (43 20 ff f8|f8 ff 20 43) bc 25,lt,0x40
4c: (41 80 00 04|04 00 80 41) bc 12,lt,0x50
50: (4e 80 00 20|20 00 80 4e) bclr 20,lt,0
54: (4c c0 04 20|20 04 c0 4c) bcctr 6,lt,0
58: (4c 83 04 61|61 04 83 4c) bctarl 4,so,0
5c: (4c 60 00 04|04 00 60 4c) addpcis r3,0
60: (28 03 04 d2|d2 04 03 28) cmpli cr0,0,r3,1234
64: (28 23 04 d2|d2 04 23 28) cmpli cr0,1,r3,1234
68: (7c 03 20 00|00 20 03 7c) cmp cr0,0,r3,r4
6c: (7c 23 20 00|00 20 23 7c) cmp cr0,1,r3,r4
70: (7c 03 20 40|40 20 03 7c) cmpl cr0,0,r3,r4
74: (7c 23 20 40|40 20 23 7c) cmpl cr0,1,r3,r4
78: (30 64 ff d6|d6 ff 64 30) addic r3,r4,-42
7c: (54 83 80 3e|3e 80 83 54) rlwinm r3,r4,16,0,31
80: (78 83 06 a0|a0 06 83 78) rldicl r3,r4,0,58
84: (60 00 00 00|00 00 00 60) ori r0,r0,0
88: (68 00 00 00|00 00 00 68) xori r0,r0,0
8c: (7e 03 20 08|08 20 03 7e) tw 16,r3,r4
90: (7c 65 20 50|50 20 65 7c) subf r3,r5,r4
94: (7c 65 20 11|11 20 65 7c) subfc\. r3,r5,r4
98: (7c 83 00 66|66 00 83 7c) mfvsrd r3,vs4
9c: (7c 83 00 67|67 00 83 7c) mfvsrd r3,vs36
a0: (7c 6f f1 20|20 f1 6f 7c) mtcrf 255,r3
a4: (7e 03 21 ec|ec 21 03 7e) dcbtst r3,r4,16
a8: (7c e3 21 ec|ec 21 e3 7c) dcbtst r3,r4,7
ac: (7d 03 21 ec|ec 21 03 7d) dcbtst r3,r4,8
b0: (7e 23 22 2c|2c 22 23 7e) dcbt r3,r4,17
b4: (7c 68 02 a6|a6 02 68 7c) mfspr r3,8
b8: (7c 69 02 a6|a6 02 69 7c) mfspr r3,9
bc: (7c 70 43 a6|a6 43 70 7c) mtspr 272,r3
c0: (7f 7b db 78|78 db 7b 7f) or r27,r27,r27
c4: (7f de f3 78|78 f3 de 7f) or r30,r30,r30
c8: (7c 20 04 ac|ac 04 20 7c) sync 1,0
cc: (06 02 00 00|00 00 02 06) paddi r3,0,-8589934592,0
d0: (38 60 00 00|00 00 60 38)

52
gas/testsuite/gas/ppc/raw.s
View File

@ -0,0 +1,52 @@
xxmr 3,4
xxlnot 3,4
xvmovsp 3,4
vmr 3,4
mr 3,4
not 3,4
crnot 5,6
crclr 7
crset 0
crmove 1,2
xxspltd 3,4,0
xxspltd 3,4,1
xxmrghd 3,4,5
xxmrgld 3,4,5
xxswapd 3,4
vctsxs 3,4,0
li 3,123
lis 4,456
bdnz+ .-8
blt .+4
blr
bgectr-
bnutarl
lnia 3
cmplwi 3,1234
cmpldi 3,1234
cmpw 3,4
cmpd 3,4
cmplw 3,4
cmpld 3,4
subic 3,4,42
rotlwi 3,4,16
clrldi 3,4,58
nop
xnop
twlt 3,4
sub 3,4,5
subc. 3,4,5
mffprd 3,4
mfvrd 3,4
mtcr 3
dcbtstt 3,4
dcbtstct 3,4,7
dcbtstds 3,4,8
dcbna 3,4
mflr 3
mfctr 3
mtsprg0 3
yield
mdoom
lwsync
pli 3,-1<<33

15
opcodes/ChangeLog
View File

@ -1,3 +1,18 @@
2021-05-29 Alan Modra <amodra@gmail.com>
* ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
Don't special case PPC_OPCODE_RAW.
(lookup_prefix): Likewise.
(lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
(print_insn_powerpc): ..update caller.
* ppc-opc.c (EXT): Define.
(powerpc_opcodes): Mark extended mnemonics with EXT.
(prefix_opcodes, vle_opcodes): Likewise.
(XISEL, XISEL_MASK): Add cr field and simplify.
(powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
all isel variants to where the base mnemonic belongs. Sort dstt,
dststt and dssall.
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,

48
opcodes/ppc-dis.c
View File

@ -580,7 +580,7 @@ skip_optional_operands (const unsigned char *opindex,
static const struct powerpc_opcode *
lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_opcode *opcode, *opcode_end, *last;
const struct powerpc_opcode *opcode, *opcode_end;
unsigned long op;
/* Get the major opcode of the instruction. */
@ -588,7 +588,6 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
/* Find the first match in the opcode table for this major opcode. */
opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
last = NULL;
for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
opcode < opcode_end;
++opcode)
@ -599,8 +598,8 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
if ((insn & opcode->mask) != opcode->opcode
|| ((dialect & PPC_OPCODE_ANY) == 0
&& ((opcode->flags & dialect) == 0
|| (opcode->deprecated & dialect) != 0)))
&& (opcode->flags & dialect) == 0)
|| (opcode->deprecated & dialect) != 0)
continue;
/* Check validity of operands. */
@ -614,16 +613,10 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
if (invalid)
continue;
if ((dialect & PPC_OPCODE_RAW) == 0)
return opcode;
/* The raw machine insn is one that is not a specialization. */
if (last == NULL
|| (last->mask & ~opcode->mask) != 0)
last = opcode;
return opcode;
}
return last;
return NULL;
}
/* Find a match for INSN in the PREFIX opcode table. */
@ -631,7 +624,7 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
static const struct powerpc_opcode *
lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_opcode *opcode, *opcode_end, *last;
const struct powerpc_opcode *opcode, *opcode_end;
unsigned long seg;
/* Get the opcode segment of the instruction. */
@ -639,7 +632,6 @@ lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
/* Find the first match in the opcode table for this major opcode. */
opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
last = NULL;
for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
opcode < opcode_end;
++opcode)
@ -650,8 +642,8 @@ lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
if ((insn & opcode->mask) != opcode->opcode
|| ((dialect & PPC_OPCODE_ANY) == 0
&& ((opcode->flags & dialect) == 0
|| (opcode->deprecated & dialect) != 0)))
&& (opcode->flags & dialect) == 0)
|| (opcode->deprecated & dialect) != 0)
continue;
/* Check validity of operands. */
@ -665,22 +657,16 @@ lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
if (invalid)
continue;
if ((dialect & PPC_OPCODE_RAW) == 0)
return opcode;
/* The raw machine insn is one that is not a specialization. */
if (last == NULL
|| (last->mask & ~opcode->mask) != 0)
last = opcode;
return opcode;
}
return last;
return NULL;
}
/* Find a match for INSN in the VLE opcode table. */
static const struct powerpc_opcode *
lookup_vle (uint64_t insn)
lookup_vle (uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_opcode *opcode;
const struct powerpc_opcode *opcode_end;
@ -711,7 +697,8 @@ lookup_vle (uint64_t insn)
insn2 = insn;
if (table_op_is_short)
insn2 >>= 16;
if ((insn2 & table_mask) != table_opcd)
if ((insn2 & table_mask) != table_opcd
|| (opcode->deprecated & dialect) != 0)
continue;
/* Check validity of operands. */
@ -734,7 +721,7 @@ lookup_vle (uint64_t insn)
/* Find a match for INSN in the SPE2 opcode table. */
static const struct powerpc_opcode *
lookup_spe2 (uint64_t insn)
lookup_spe2 (uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_opcode *opcode, *opcode_end;
unsigned op, xop, seg;
@ -763,7 +750,8 @@ lookup_spe2 (uint64_t insn)
int invalid;
insn2 = insn;
if ((insn2 & table_mask) != table_opcd)
if ((insn2 & table_mask) != table_opcd
|| (opcode->deprecated & dialect) != 0)
continue;
/* Check validity of operands. */
@ -916,7 +904,7 @@ print_insn_powerpc (bfd_vma memaddr,
}
if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
{
opcode = lookup_vle (insn);
opcode = lookup_vle (insn, dialect);
if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
{
/* The operands will be fetched out of the 16-bit instruction. */
@ -927,7 +915,7 @@ print_insn_powerpc (bfd_vma memaddr,
if (opcode == NULL && insn_length == 4)
{
if ((dialect & PPC_OPCODE_SPE2) != 0)
opcode = lookup_spe2 (insn);
opcode = lookup_spe2 (insn, dialect);
if (opcode == NULL)
opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)

3206
opcodes/ppc-opc.c
View File

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