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gas/ 

2009-01-09  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .rdtscp.
	(md_show_usage): Display rdtscp.

	* doc/c-i386.texi: Document rdtscp.

gas/testsuite/

2009-01-09  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10.s: Add rdtscp.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2009-01-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
	and CPU_AMDFAM10_FLAGS.  Add CPU_RDTSCP_FLAGS.
	(cpu_flags): Add CpuRdtscp.
	(set_bitfield): Remove CpuSledgehammer check.

	* i386-opc.h (CpuRdtscp): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpurdtscp.

	* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
cgen-1_1-branch
H.J. Lu 18 years ago
parent
1cb0a76746
commit
1b7f3fb0dd
18 changed files with 2656 additions and 2586 deletions
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  1. 7
      gas/ChangeLog
  2. 5
      gas/config/tc-i386.c
  3. 3
      gas/doc/c-i386.texi
  4. 12
      gas/testsuite/ChangeLog
  5. 31
      gas/testsuite/gas/i386/arch-10-1.l
  6. 31
      gas/testsuite/gas/i386/arch-10-2.l
  7. 34
      gas/testsuite/gas/i386/arch-10-3.l
  8. 34
      gas/testsuite/gas/i386/arch-10-4.l
  9. 3
      gas/testsuite/gas/i386/arch-10.d
  10. 2
      gas/testsuite/gas/i386/arch-10.s
  11. 3
      gas/testsuite/gas/i386/x86-64-arch-2.d
  12. 2
      gas/testsuite/gas/i386/x86-64-arch-2.s
  13. 15
      opcodes/ChangeLog
  14. 11
      opcodes/i386-gen.c
  15. 92
      opcodes/i386-init.h
  16. 5
      opcodes/i386-opc.h
  17. 2
      opcodes/i386-opc.tbl
  18. 4950
      opcodes/i386-tbl.h

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .rdtscp.
(md_show_usage): Display rdtscp.
* doc/c-i386.texi: Document rdtscp.
2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
* config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test.

5
gas/config/tc-i386.c
View File

@ -650,6 +650,8 @@ static const arch_entry cpu_arch[] =
CPU_MOVBE_FLAGS },
{ ".ept", PROCESSOR_UNKNOWN,
CPU_EPT_FLAGS },
{ ".rdtscp", PROCESSOR_UNKNOWN,
CPU_RDTSCP_FLAGS },
{ ".3dnow", PROCESSOR_UNKNOWN,
CPU_3DNOW_FLAGS },
{ ".3dnowa", PROCESSOR_UNKNOWN,
@ -8235,7 +8237,8 @@ md_show_usage (stream)
EXTENSION is combination of:\n\
mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\
padlock\n"));
fprintf (stream, _("\
-mtune=CPU optimize for CPU, CPU is one of:\n\
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\

3
gas/doc/c-i386.texi
View File

@ -130,6 +130,7 @@ accept various extension mnemonics. For example,
@code{fma},
@code{movbe},
@code{ept},
@code{rdtscp},
@code{3dnow},
@code{3dnowa},
@code{sse4a},
@ -879,7 +880,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
@item @samp{.ept}
@item @samp{.ept} @tab @samp{.rdtscp}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.svme} @tab @samp{.abm}
@item @samp{.padlock}

12
gas/testsuite/ChangeLog
View File

@ -1,3 +1,15 @@
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add rdtscp.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
2009-01-06 Chao-ying Fu <fu@mips.com>
* gas/mips/jalr.s, gas/mips/jalr.l: Add more tests for jalr

31
gas/testsuite/gas/i386/arch-10-1.l
View File

@ -24,6 +24,7 @@
.*:48: Error: .*
.*:50: Error: .*
.*:52: Error: .*
.*:54: Error: .*
GAS LISTING .*
@ -66,17 +67,19 @@ GAS LISTING .*
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*38[ ]+invept \(%ecx\),%ebx
[ ]*39[ ]+\# 3DNow
[ ]*40[ ]+pmulhrw %mm4,%mm3
[ ]*41[ ]+\# 3DNow Extensions
[ ]*42[ ]+pswapd %mm4,%mm3
[ ]*43[ ]+\# SSE4a
[ ]*44[ ]+insertq %xmm2,%xmm1
[ ]*45[ ]+\# SVME
[ ]*46[ ]+vmload
[ ]*47[ ]+\# ABM
[ ]*48[ ]+lzcnt %ecx,%ebx
[ ]*49[ ]+\# SSE5
[ ]*50[ ]+frczss %xmm2, %xmm1
[ ]*51[ ]+\# PadLock
[ ]*52[ ]+xstorerng
[ ]*39[ ]+\# RDTSCP
[ ]*40[ ]+rdtscp
[ ]*41[ ]+\# 3DNow
[ ]*42[ ]+pmulhrw %mm4,%mm3
[ ]*43[ ]+\# 3DNow Extensions
[ ]*44[ ]+pswapd %mm4,%mm3
[ ]*45[ ]+\# SSE4a
[ ]*46[ ]+insertq %xmm2,%xmm1
[ ]*47[ ]+\# SVME
[ ]*48[ ]+vmload
[ ]*49[ ]+\# ABM
[ ]*50[ ]+lzcnt %ecx,%ebx
[ ]*51[ ]+\# SSE5
[ ]*52[ ]+frczss %xmm2, %xmm1
[ ]*53[ ]+\# PadLock
[ ]*54[ ]+xstorerng

31
gas/testsuite/gas/i386/arch-10-2.l
View File

@ -23,6 +23,7 @@
.*:48: Error: .*
.*:50: Error: .*
.*:52: Error: .*
.*:54: Error: .*
GAS LISTING .*
@ -65,17 +66,19 @@ GAS LISTING .*
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*38[ ]+invept \(%ecx\),%ebx
[ ]*39[ ]+\# 3DNow
[ ]*40[ ]+pmulhrw %mm4,%mm3
[ ]*41[ ]+\# 3DNow Extensions
[ ]*42[ ]+pswapd %mm4,%mm3
[ ]*43[ ]+\# SSE4a
[ ]*44[ ]+insertq %xmm2,%xmm1
[ ]*45[ ]+\# SVME
[ ]*46[ ]+vmload
[ ]*47[ ]+\# ABM
[ ]*48[ ]+lzcnt %ecx,%ebx
[ ]*49[ ]+\# SSE5
[ ]*50[ ]+frczss %xmm2, %xmm1
[ ]*51[ ]+\# PadLock
[ ]*52[ ]+xstorerng
[ ]*39[ ]+\# RDTSCP
[ ]*40[ ]+rdtscp
[ ]*41[ ]+\# 3DNow
[ ]*42[ ]+pmulhrw %mm4,%mm3
[ ]*43[ ]+\# 3DNow Extensions
[ ]*44[ ]+pswapd %mm4,%mm3
[ ]*45[ ]+\# SSE4a
[ ]*46[ ]+insertq %xmm2,%xmm1
[ ]*47[ ]+\# SVME
[ ]*48[ ]+vmload
[ ]*49[ ]+\# ABM
[ ]*50[ ]+lzcnt %ecx,%ebx
[ ]*51[ ]+\# SSE5
[ ]*52[ ]+frczss %xmm2, %xmm1
[ ]*53[ ]+\# PadLock
[ ]*54[ ]+xstorerng

34
gas/testsuite/gas/i386/arch-10-3.l
View File

@ -16,6 +16,7 @@
.*:48: Error: .*
.*:50: Error: .*
.*:52: Error: .*
.*:54: Error: .*
GAS LISTING .*
@ -61,17 +62,22 @@ GAS LISTING .*
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*38[ ]+invept \(%ecx\),%ebx
[ ]*39[ ]+\# 3DNow
[ ]*40[ ]+pmulhrw %mm4,%mm3
[ ]*41[ ]+\# 3DNow Extensions
[ ]*42[ ]+pswapd %mm4,%mm3
[ ]*43[ ]+\# SSE4a
[ ]*44[ ]+insertq %xmm2,%xmm1
[ ]*45[ ]+\# SVME
[ ]*46[ ]+vmload
[ ]*47[ ]+\# ABM
[ ]*48[ ]+lzcnt %ecx,%ebx
[ ]*49[ ]+\# SSE5
[ ]*50[ ]+frczss %xmm2, %xmm1
[ ]*51[ ]+\# PadLock
[ ]*52[ ]+xstorerng
[ ]*39[ ]+\# RDTSCP
[ ]*40[ ]+rdtscp
[ ]*41[ ]+\# 3DNow
[ ]*42[ ]+pmulhrw %mm4,%mm3
[ ]*43[ ]+\# 3DNow Extensions
[ ]*44[ ]+pswapd %mm4,%mm3
[ ]*45[ ]+\# SSE4a
[ ]*46[ ]+insertq %xmm2,%xmm1
[ ]*47[ ]+\# SVME
[ ]*48[ ]+vmload
[ ]*49[ ]+\# ABM
[ ]*50[ ]+lzcnt %ecx,%ebx
[ ]*51[ ]+\# SSE5
[ ]*52[ ]+frczss %xmm2, %xmm1
[ ]*53[ ]+\# PadLock
GAS LISTING .*
[ ]*54[ ]+xstorerng

34
gas/testsuite/gas/i386/arch-10-4.l
View File

@ -14,6 +14,7 @@
.*:48: Error: .*
.*:50: Error: .*
.*:52: Error: .*
.*:54: Error: .*
GAS LISTING .*
@ -59,17 +60,22 @@ GAS LISTING .*
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*38[ ]+invept \(%ecx\),%ebx
[ ]*39[ ]+\# 3DNow
[ ]*40[ ]+pmulhrw %mm4,%mm3
[ ]*41[ ]+\# 3DNow Extensions
[ ]*42[ ]+pswapd %mm4,%mm3
[ ]*43[ ]+\# SSE4a
[ ]*44[ ]+insertq %xmm2,%xmm1
[ ]*45[ ]+\# SVME
[ ]*46[ ]+vmload
[ ]*47[ ]+\# ABM
[ ]*48[ ]+lzcnt %ecx,%ebx
[ ]*49[ ]+\# SSE5
[ ]*50[ ]+frczss %xmm2, %xmm1
[ ]*51[ ]+\# PadLock
[ ]*52[ ]+xstorerng
[ ]*39[ ]+\# RDTSCP
[ ]*40[ ]+rdtscp
[ ]*41[ ]+\# 3DNow
[ ]*42[ ]+pmulhrw %mm4,%mm3
[ ]*43[ ]+\# 3DNow Extensions
[ ]*44[ ]+pswapd %mm4,%mm3
[ ]*45[ ]+\# SSE4a
[ ]*46[ ]+insertq %xmm2,%xmm1
[ ]*47[ ]+\# SVME
[ ]*48[ ]+vmload
[ ]*49[ ]+\# ABM
[ ]*50[ ]+lzcnt %ecx,%ebx
[ ]*51[ ]+\# SSE5
[ ]*52[ ]+frczss %xmm2, %xmm1
[ ]*53[ ]+\# PadLock
GAS LISTING .*
[ ]*54[ ]+xstorerng

3
gas/testsuite/gas/i386/arch-10.d
View File

@ -1,4 +1,4 @@
#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+sse5+3dnowa+svme+padlock
#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+rdtscp+sse5+3dnowa+svme+padlock
#objdump: -dw
#name: i386 arch 10
@ -25,6 +25,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1

2
gas/testsuite/gas/i386/arch-10.s
View File

@ -36,6 +36,8 @@ vfmadd132pd %xmm4,%xmm6,%xmm2
movbe (%ecx),%ebx
# EPT
invept (%ecx),%ebx
# RDTSCP
rdtscp
# 3DNow
pmulhrw %mm4,%mm3
# 3DNow Extensions

3
gas/testsuite/gas/i386/x86-64-arch-2.d
View File

@ -1,4 +1,4 @@
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+sse5+3dnowa+svme+padlock
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+rdtscp+sse5+3dnowa+svme+padlock
#objdump: -dw
#name: x86-64 arch 2
@ -25,6 +25,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1

2
gas/testsuite/gas/i386/x86-64-arch-2.s
View File

@ -36,6 +36,8 @@ vfmadd132pd %xmm4,%xmm6,%xmm2
movbe (%rcx),%ebx
# EPT
invept (%rcx),%rbx
# RDTSCP
rdtscp
# 3DNow
pmulhrw %mm4,%mm3
# 3DNow Extensions

15
opcodes/ChangeLog
View File

@ -1,3 +1,18 @@
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS.
(cpu_flags): Add CpuRdtscp.
(set_bitfield): Remove CpuSledgehammer check.
* i386-opc.h (CpuRdtscp): New.
(CpuLM): Updated.
(i386_cpu_flags): Add cpurdtscp.
* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c (PPCNONE): Define.

11
opcodes/i386-gen.c
View File

@ -81,9 +81,9 @@ static initializer cpu_flag_init [] =
{ "CPU_ATHLON_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuMMX|Cpu3dnow|Cpu3dnowA" },
{ "CPU_K8_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuRdtscp|CpuLM" },
{ "CPU_AMDFAM10_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuRdtscp|CpuLM" },
{ "CPU_MMX_FLAGS",
"CpuMMX" },
{ "CPU_SSE_FLAGS",
@ -112,6 +112,8 @@ static initializer cpu_flag_init [] =
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
{ "CPU_MOVBE_FLAGS",
"CpuMovbe" },
{ "CPU_RDTSCP_FLAGS",
"CpuRdtscp" },
{ "CPU_EPT_FLAGS",
"CpuEPT" },
{ "CPU_3DNOW_FLAGS",
@ -274,6 +276,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuLM),
BITFIELD (CpuMovbe),
BITFIELD (CpuEPT),
BITFIELD (CpuRdtscp),
BITFIELD (Cpu64),
BITFIELD (CpuNo64),
#ifdef CpuUnused
@ -500,9 +503,7 @@ set_bitfield (const char *f, bitfield *array, unsigned int size)
{
unsigned int i;
if (strcmp (f, "CpuSledgehammer") == 0)
f= "CpuK8";
else if (strcmp (f, "Mmword") == 0)
if (strcmp (f, "Mmword") == 0)
f= "Qword";
else if (strcmp (f, "Oword") == 0)
f= "Xmmword";

92
opcodes/i386-init.h
View File

@ -21,179 +21,183 @@
#define CPU_UNKNOWN_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_GENERIC32_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_GENERIC64_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_NONE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I186_FLAGS \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I286_FLAGS \
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I386_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I486_FLAGS \
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I586_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I686_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P4_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NOCONA_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_CORE_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CORE2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_K6_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K6_2_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ATHLON_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K8_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
#define CPU_AMDFAM10_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
#define CPU_MMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AES_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PCLMUL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FMA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MOVBE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDTSCP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
#define CPU_EPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
#define CPU_3DNOW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_3DNOWA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PADLOCK_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SVME_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4A_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ABM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE5_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_NONE \

5
opcodes/i386-opc.h
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@ -94,8 +94,10 @@
#define CpuMovbe (CpuFMA + 1)
/* EPT Instructions required */
#define CpuEPT (CpuMovbe + 1)
/* RDTSCP Instuction support required */
#define CpuRdtscp (CpuEPT + 1)
/* 64bit support available, used by -march= in assembler. */
#define CpuLM (CpuEPT + 1)
#define CpuLM (CpuRdtscp + 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
@ -150,6 +152,7 @@ typedef union i386_cpu_flags
unsigned int cpufma:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;

2
opcodes/i386-opc.tbl
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@ -2493,7 +2493,7 @@ syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
sysret, 0, 0xf07, None, 2, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
swapgs, 0, 0xf01, 0xf8, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
rdtscp, 0, 0xf01, 0xf9, 2, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
rdtscp, 0, 0xf01, 0xf9, 2, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
// AMD Pacifica additions.
clgi, 0, 0xf01, 0xdd, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }

4950
opcodes/i386-tbl.h
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