RISC-V: Accept constant operands in la and lla

opcodes/
	PR gas/23305
	* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
	la and lla.

gas/
	PR gas/23305
	* config/tc-riscv.c (riscv_ip): Add format specifier 'B' for
	constants and symbols.
	* testsuite/gas/riscv/lla32.d: New file.
	* testsuite/gas/riscv/lla32.s: Likewise.
	* testsuite/gas/riscv/lla64-fail.d: Likewise.
	* testsuite/gas/riscv/lla64-fail.l: Likewise.
	* testsuite/gas/riscv/lla64-fail.s: Likewise.
	* testsuite/gas/riscv/lla64.d: Likewise.
	* testsuite/gas/riscv/lla64.s: Likewise.

gas/ChangeLog

@@ -1,3 +1,16 @@
+2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+	PR gas/23305
+	* config/tc-riscv.c (riscv_ip): Add format specifier 'B' for
+	constants and symbols.
+	* testsuite/gas/riscv/lla32.d: New file.
+	* testsuite/gas/riscv/lla32.s: Likewise.
+	* testsuite/gas/riscv/lla64-fail.d: Likewise.
+	* testsuite/gas/riscv/lla64-fail.l: Likewise.
+	* testsuite/gas/riscv/lla64-fail.s: Likewise.
+	* testsuite/gas/riscv/lla64.d: Likewise.
+	* testsuite/gas/riscv/lla64.s: Likewise.
+
 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.

gas/config/tc-riscv.c

@@ -1935,6 +1935,17 @@ rvc_lui:
 	      s = expr_end;
 	      continue;
 
+	    case 'B':
+	      my_getExpression (imm_expr, s);
+	      normalize_constant_expr (imm_expr);
+	      /* The 'B' format specifier must be a symbol or a constant.  */
+	      if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
+	        break;
+	      if (imm_expr->X_op == O_symbol)
+	        *imm_reloc = BFD_RELOC_32;
+	      s = expr_end;
+	      continue;
+
 	    case 'j': /* Sign-extended immediate.  */
 	      *imm_reloc = BFD_RELOC_RISCV_LO12_I;
 	      p = percent_op_itype;

gas/testsuite/gas/riscv/lla32.d

@@ -0,0 +1,19 @@
+#as: -march=rv32i -mabi=ilp32
+#objdump: -dr
+
+.*:     file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+   0:	00100513          	li	a0,1
+   4:	00001537          	lui	a0,0x1
+   8:	00001537          	lui	a0,0x1
+   c:	00150513          	addi	a0,a0,1 # 1001 <c>
+  10:	00001537          	lui	a0,0x1
+  14:	fff50513          	addi	a0,a0,-1 # fff <d>
+  18:	80000537          	lui	a0,0x80000
+  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>
+  20:	00000513          	li	a0,0
+  24:	fff00513          	li	a0,-1

gas/testsuite/gas/riscv/lla32.s

@@ -0,0 +1,15 @@
+.set a, 0x1
+.set b, 0x1000
+.set c, 0x1001
+.set d, 0xfff
+.set e, 0x7fffffff
+.set g, 0x0
+.set h, 0xffffffff
+.text
+	lla a0, a
+	lla a0, b
+	lla a0, c
+	lla a0, d
+	lla a0, e
+	lla a0, g
+	lla a0, h

gas/testsuite/gas/riscv/lla64-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv64i -mabi=lp64
+#source: lla64-fail.s
+#error-output: lla64-fail.l

gas/testsuite/gas/riscv/lla64-fail.l

@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: offset too large

gas/testsuite/gas/riscv/lla64-fail.s

@@ -0,0 +1,3 @@
+.set a, 0xffffffff
+.text
+	lla a0, a

gas/testsuite/gas/riscv/lla64.d

@@ -0,0 +1,20 @@
+#as: -march=rv64i -mabi=lp64
+#objdump: -dr
+
+.*:     file format elf64-littleriscv
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+   0:	0010051b          	addiw	a0,zero,1
+   4:	00001537          	lui	a0,0x1
+   8:	00001537          	lui	a0,0x1
+   c:	0015051b          	addiw	a0,a0,1
+  10:	00001537          	lui	a0,0x1
+  14:	fff5051b          	addiw	a0,a0,-1
+  18:	80000537          	lui	a0,0x80000
+  1c:	fff5051b          	addiw	a0,a0,-1
+  20:	0000051b          	sext.w	a0,zero
+  24:	fff0051b          	addiw	a0,zero,-1
+  28:	80000537          	lui	a0,0x80000

gas/testsuite/gas/riscv/lla64.s

@@ -0,0 +1,17 @@
+.set a, 0x1
+.set b, 0x1000
+.set c, 0x1001
+.set d, 0xfff
+.set e, 0x7fffffff
+.set g, 0x0
+.set h, 0xffffffffffffffff
+.set i, 0xffffffff80000000
+.text
+	lla a0, a
+	lla a0, b
+	lla a0, c
+	lla a0, d
+	lla a0, e
+	lla a0, g
+	lla a0, h
+	lla a0, i

opcodes/ChangeLog

@@ -1,3 +1,9 @@
+2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+	PR gas/23305
+	* riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
+	la and lla.
+
 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.

opcodes/riscv-opc.c

@@ -278,8 +278,8 @@ const struct riscv_opcode riscv_opcodes[] =
    applied to an add instruction, for relaxation to use.  */
 {"add",       "I",   "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
 {"add",       "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
-{"la",        "I",   "d,A",  0,    (int) M_LA,  match_never, INSN_MACRO },
-{"lla",       "I",   "d,A",  0,    (int) M_LLA,  match_never, INSN_MACRO },
+{"la",        "I",   "d,B",  0,    (int) M_LA,  match_never, INSN_MACRO },
+{"lla",       "I",   "d,B",  0,    (int) M_LLA,  match_never, INSN_MACRO },
 {"la.tls.gd", "I",   "d,A",  0,    (int) M_LA_TLS_GD,  match_never, INSN_MACRO },
 {"la.tls.ie", "I",   "d,A",  0,    (int) M_LA_TLS_IE,  match_never, INSN_MACRO },
 {"neg",       "I",   "d,t",  MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */