Correct ordering of args for cmov insn.

29 years ago · 1379884be1
2 changed files with 7 additions and 1 deletions
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@ -1,3 +1,9 @@
+start-sanitize-v850e
+Fri Sep 19 11:45:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
+
+end-sanitize-v850e
 Thu Sep 18 11:21:43 1997  Doug Evans  <dje@canuck.cygnus.com>

 	* sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@ -638,7 +638,7 @@ const struct v850_opcode v850_opcodes[] =
 /* arithmetic operation instructions */
 { "setf",	two (0x07e0, 0x0000),	two (0x07f0, 0xffff), 	{CCCC, R2}, 		0, PROCESSOR_ALL },
 /* start-sanitize-v850e */
-{ "cmov",	two (0x07e0, 0x0320),	two (0x07e0, 0x07e1), 	{MOVCC, R2, R1, R3}, 	0, PROCESSOR_NOT_V850 },
+{ "cmov",	two (0x07e0, 0x0320),	two (0x07e0, 0x07e1), 	{MOVCC, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 },
 { "cmov",	two (0x07e0, 0x0300),	two (0x07e0, 0x07e1), 	{MOVCC, I5, R2, R3}, 	0, PROCESSOR_NOT_V850 },

 { "mul",	two (0x07e0, 0x0220),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_NOT_V850 },