@ -1925,6 +1925,11 @@ CGEN_GEN_CPU_DESC = \
$( @D) " $$ FLAGS " $$ cpu " $$ isa " $$ mach " $$ SUFFIX " \
$( CGEN_ARCHFILE) ignored $$ opcfile
CGEN_GEN_MLOOP = \
$( SHELL) $( srccom) /genmloop.sh \
-shell $( SHELL) \
-infile $< -outfile-prefix $( @D) /
# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@ -4998,21 +5003,19 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c : | $( cris_BUILD_OUTPUTS )
@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv10f.c cris/engv10.h : cris /stamp -mloop -v 10f ; @true
@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f : $( srccom ) /genmloop .sh cris /mloop .in
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f : cris /mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - m o n o - n o - f a s t - p b b - s w i t c h s e m c r i s v 1 0 f - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - c p u c r i s v 1 0 f \
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - i n f i l e $( srcdir ) / c r i s / m l o o p . i n - o u t f i l e - p r e f i x c r i s / - o u t f i l e - s u f f i x - v 1 0 f
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - c p u c r i s v 1 0 f - o u t f i l e - s u f f i x - v 1 0 f
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e c r i s / e n g - v 1 0 f . h i n c r i s / e n g v 1 0 . h
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e c r i s / m l o o p - v 1 0 f . c i n c r i s / m l o o p v 1 0 f . c
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_at ) t o u c h $@
@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv32f.c cris/engv32.h : cris /stamp -mloop -v 32f ; @true
@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f : $( srccom ) /genmloop .sh cris /mloop .in
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f : cris /mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - m o n o - n o - f a s t - p b b - s w i t c h s e m c r i s v 3 2 f - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - c p u c r i s v 3 2 f \
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - i n f i l e $( srcdir ) / c r i s / m l o o p . i n - o u t f i l e - p r e f i x c r i s / - o u t f i l e - s u f f i x - v 3 2 f
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ - c p u c r i s v 3 2 f - o u t f i l e - s u f f i x - v 3 2 f
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e c r i s / e n g - v 3 2 f . h i n c r i s / e n g v 3 2 . h
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e c r i s / m l o o p - v 3 2 f . c i n c r i s / m l o o p v 3 2 f . c
@ S I M _ E N A B L E _ A R C H _ c r i s _ T R U E @ $( AM_V_at ) t o u c h $@
@ -5087,11 +5090,10 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c : | $( frv_BUILD_OUTPUTS )
@SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h : frv /stamp -mloop ; @true
@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop : $( srccom ) /genmloop .sh frv /mloop .in
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop : frv /mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ - m o n o - s c a c h e - p a r a l l e l - g e n e r i c - w r i t e - p a r a l l e l - o n l y \
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ - c p u f r v b f \
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ - i n f i l e $( srcdir ) / f r v / m l o o p . i n - o u t f i l e - p r e f i x f r v /
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ - c p u f r v b f
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e f r v / e n g . h i n f r v / e n g . h
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e f r v / m l o o p . c i n f r v / m l o o p . c
@ S I M _ E N A B L E _ A R C H _ f r v _ T R U E @ $( AM_V_at ) t o u c h $@
@ -5127,11 +5129,10 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c : | $( iq 2000_BUILD_OUTPUTS )
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h : iq 2000/stamp -mloop ; @true
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop : $( srccom ) /genmloop .sh iq 2000/mloop .in
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop : iq 2000/mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ - m o n o - f a s t - p b b - s w i t c h s e m - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ - c p u i q 2 0 0 0 b f \
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ - i n f i l e $( srcdir ) / i q 2 0 0 0 / m l o o p . i n - o u t f i l e - p r e f i x i q 2 0 0 0 /
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ - c p u i q 2 0 0 0 b f
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e i q 2 0 0 0 / e n g . h i n i q 2 0 0 0 / e n g . h
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e i q 2 0 0 0 / m l o o p . c i n i q 2 0 0 0 / m l o o p . c
@ S I M _ E N A B L E _ A R C H _ i q 2 0 0 0 _ T R U E @ $( AM_V_at ) t o u c h $@
@ -5155,11 +5156,10 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c : | $( lm 32_BUILD_OUTPUTS )
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h : lm 32/stamp -mloop ; @true
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop : $( srccom ) /genmloop .sh lm 32/mloop .in
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop : lm 32/mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ - m o n o - f a s t - p b b - s w i t c h s e m - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ - c p u l m 3 2 b f \
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ - i n f i l e $( srcdir ) / l m 3 2 / m l o o p . i n - o u t f i l e - p r e f i x l m 3 2 /
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ - c p u l m 3 2 b f
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e l m 3 2 / e n g . h i n l m 3 2 / e n g . h
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e l m 3 2 / m l o o p . c i n l m 3 2 / m l o o p . c
@ S I M _ E N A B L E _ A R C H _ l m 3 2 _ T R U E @ $( AM_V_at ) t o u c h $@
@ -5207,31 +5207,28 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c : | $( m 32r_BUILD_OUTPUTS )
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h : m 32r /stamp -mloop ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop : $( srccom ) /genmloop .sh m 32r /mloop .in
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop : m 32r /mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - m o n o - f a s t - p b b - s w i t c h s e m - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - c p u m 3 2 r b f \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - i n f i l e $( srcdir ) / m 3 2 r / m l o o p . i n - o u t f i l e - p r e f i x m 3 2 r /
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - c p u m 3 2 r b f
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e m 3 2 r / e n g . h i n m 3 2 r / e n g . h
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e m 3 2 r / m l o o p . c i n m 3 2 r / m l o o p . c
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) t o u c h $@
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h : m 32r /stamp -mloop -x ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x : $( srccom ) /genmloop .sh m 32r /mloopx .in
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x : m 32r /mloopx .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - m o n o - n o - f a s t - p b b - p a r a l l e l - w r i t e - s w i t c h s e m x - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - c p u m 3 2 r x f \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - i n f i l e $( srcdir ) / m 3 2 r / m l o o p x . i n - o u t f i l e - p r e f i x m 3 2 r / - o u t f i l e - s u f f i x x
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - c p u m 3 2 r x f - o u t f i l e - s u f f i x x
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e m 3 2 r / e n g x . h i n m 3 2 r / e n g x . h
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e m 3 2 r / m l o o p x . c i n m 3 2 r / m l o o p x . c
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) t o u c h $@
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h : m 32r /stamp -mloop -2 ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2 : $( srccom ) /genmloop .sh m 32r /mloop 2.in
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2 : m 32r /mloop 2.in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - m o n o - n o - f a s t - p b b - p a r a l l e l - w r i t e - s w i t c h s e m 2 - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - c p u m 3 2 r 2 f \
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - i n f i l e $( srcdir ) / m 3 2 r / m l o o p 2 . i n - o u t f i l e - p r e f i x m 3 2 r / - o u t f i l e - s u f f i x 2
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ - c p u m 3 2 r 2 f - o u t f i l e - s u f f i x 2
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e m 3 2 r / e n g 2 . h i n m 3 2 r / e n g 2 . h
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e m 3 2 r / m l o o p 2 . c i n m 3 2 r / m l o o p 2 . c
@ S I M _ E N A B L E _ A R C H _ m 3 2 r _ T R U E @ $( AM_V_at ) t o u c h $@
@ -5563,11 +5560,10 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c : | $( or 1k_BUILD_OUTPUTS )
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h : or 1k /stamp -mloop ; @true
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop : $( srccom ) /genmloop .sh or 1k /mloop .in
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ $( AM_V_GEN ) $( SHELL ) $( srccom ) / g e n m l o o p . s h - s h e l l $( SHELL ) \
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop : or 1k /mloop .in $( srccom ) /genmloop .sh
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ $( AM_V_GEN ) $( CGEN_GEN_MLOOP ) \
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ - m o n o - f a s t - p b b - s w i t c h s e m - s w i t c h . c \
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ - c p u o r 1 k 3 2 b f \
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ - i n f i l e $( srcdir ) / o r 1 k / m l o o p . i n - o u t f i l e - p r e f i x o r 1 k /
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ - c p u o r 1 k 3 2 b f
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e o r 1 k / e n g . h i n o r 1 k / e n g . h
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ $( AM_V_at ) $( SHELL ) $( srcroot ) / m o v e - i f - c h a n g e o r 1 k / m l o o p . c i n o r 1 k / m l o o p . c
@ S I M _ E N A B L E _ A R C H _ o r 1 k _ T R U E @ $( AM_V_at ) t o u c h $@