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Support APX Push2/Pop2 

PPX functionality for PUSH/POP is not implemented in this patch
and will be implemented separately.

gas/ChangeLog:

2023-12-28  Zewei Mo <zewei.mo@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>
            Lili Cui <lili.cui@intel.com>

	* config/tc-i386.c: (enum i386_error):
	New unsupported_rsp_register and invalid_src_register_set.
	(md_assemble): Add handler for unsupported_rsp_register and
	invalid_src_register_set.
	(check_APX_operands): Add invalid check for push2/pop2.
	(match_template): Handle check_APX_operands.
	* testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2.d: New test.
	* testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto.
	* testsuite/gas/i386/apx-push2pop2-inval.s: Ditto.
	* testsuite/gas/i386/apx-push2pop2-inval.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad
	testcases for POP2.
	* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.

opcodes/ChangeLog:

	* i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F.
	* i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6
	* i386-dis-evex.h: Add REG_EVEX_MAP4_8F.
	* i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2.
	(get_valid_dis386): Add handler for vector length and address_mode for
	APX-Push2/Pop2 insn.
	(nd): define nd as b for EVEX-promoted instrutions.
	(OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn.
	* i386-gen.c: Add Push2Pop2 bitfield.
	* i386-opc.h: Regenerated.
	* i386-opc.tbl: Regenerated.
binutils-2_42-branch
Mo, Zewei 3 years ago
committed by Cui, Lili
parent
3083f37643
commit
08a98d4c13
19 changed files with 2291 additions and 1960 deletions
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  1. 44
      gas/config/tc-i386.c
  2. 5
      gas/testsuite/gas/i386/apx-push2pop2-inval.l
  3. 9
      gas/testsuite/gas/i386/apx-push2pop2-inval.s
  4. 1
      gas/testsuite/gas/i386/i386.exp
  5. 5
      gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
  6. 7
      gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
  7. 42
      gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d
  8. 13
      gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l
  9. 17
      gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s
  10. 42
      gas/testsuite/gas/i386/x86-64-apx-push2pop2.d
  11. 39
      gas/testsuite/gas/i386/x86-64-apx-push2pop2.s
  12. 3
      gas/testsuite/gas/i386/x86-64.exp
  13. 9
      opcodes/i386-dis-evex-reg.h
  14. 10
      opcodes/i386-dis-evex-w.h
  15. 2
      opcodes/i386-dis-evex.h
  16. 31
      opcodes/i386-dis.c
  17. 3920
      opcodes/i386-mnem.h
  18. 9
      opcodes/i386-opc.tbl
  19. 43
      opcodes/i386-tbl.h

44
gas/config/tc-i386.c
View File

@ -250,6 +250,7 @@ enum i386_error
invalid_vector_register_set,
invalid_tmm_register_set,
invalid_dest_and_src_register_set,
invalid_dest_register_set,
invalid_pseudo_prefix,
unsupported_vector_index_register,
unsupported_broadcast,
@ -259,6 +260,7 @@ enum i386_error
no_default_mask,
unsupported_rc_sae,
unsupported_vector_size,
unsupported_rsp_register,
internal_error,
};
@ -5511,6 +5513,9 @@ md_assemble (char *line)
case invalid_dest_and_src_register_set:
err_msg = _("destination and source registers must be distinct");
break;
case invalid_dest_register_set:
err_msg = _("two dest registers must be distinct");
break;
case invalid_pseudo_prefix:
err_msg = _("rex2 pseudo prefix cannot be used");
break;
@ -5539,6 +5544,9 @@ md_assemble (char *line)
as_bad (_("vector size above %u required for `%s'"), 128u << vector_size,
pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
return;
case unsupported_rsp_register:
err_msg = _("'rsp' register cannot be used");
break;
case internal_error:
err_msg = _("internal error");
break;
@ -7175,6 +7183,35 @@ check_EgprOperands (const insn_template *t)
return 0;
}
/* Check if APX operands are valid for the instruction. */
static bool
check_APX_operands (const insn_template *t)
{
/* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
*/
switch (t->mnem_off)
{
case MN_pop2:
case MN_pop2p:
if (register_number (i.op[0].regs) == register_number (i.op[1].regs))
{
i.error = invalid_dest_register_set;
return 1;
}
/* fall through */
case MN_push2:
case MN_push2p:
if (register_number (i.op[0].regs) == 4
|| register_number (i.op[1].regs) == 4)
{
i.error = unsupported_rsp_register;
return 1;
}
break;
}
return 0;
}
/* Helper function for the progress() macro in match_template(). */
static INLINE enum i386_error progress (enum i386_error new,
enum i386_error last,
@ -7675,6 +7712,13 @@ match_template (char mnem_suffix)
continue;
}
/* Check if APX operands are valid. */
if (check_APX_operands (t))
{
specific_error = progress (i.error);
continue;
}
/* Check whether to use the shorter VEX encoding for certain insns where
the EVEX encoding comes first in the table. This requires the respective
AVX-* feature to be explicitly enabled.

5
gas/testsuite/gas/i386/apx-push2pop2-inval.l
View File

@ -0,0 +1,5 @@
.* Assembler messages:
.*:6: Error: `push2' is only supported in 64-bit mode
.*:7: Error: `push2p' is only supported in 64-bit mode
.*:8: Error: `pop2' is only supported in 64-bit mode
.*:9: Error: `pop2p' is only supported in 64-bit mode

9
gas/testsuite/gas/i386/apx-push2pop2-inval.s
View File

@ -0,0 +1,9 @@
# Check 32bit APX-PUSH2/POP2 instructions
.allow_index_reg
.text
_start:
push2 %rax, %rbx
push2p %rax, %rbx
pop2 %rax, %rbx
pop2p %rax, %rbx

1
gas/testsuite/gas/i386/i386.exp
View File

@ -511,6 +511,7 @@ if [gas_32_check] then {
run_dump_test "sm4-intel"
run_list_test "pbndkb-inval"
run_list_test "user_msr-inval"
run_list_test "apx-push2pop2-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"

5
gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
View File

@ -34,3 +34,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+:[ ]+62 f4 e4[ ]+\(bad\)
[ ]*[a-f0-9]+:[ ]+08 ff[ ]+.*
[ ]*[a-f0-9]+:[ ]+04 08[ ]+.*
[ ]*[a-f0-9]+:[ ]+62 f4 3c[ ]+\(bad\)
[ ]*[a-f0-9]+:[ ]+08 8f c0 ff ff ff[ ]+or.*
[ ]*[a-f0-9]+:[ ]+62 74 7c 18 8f c0[ ]+pop2 %rax,\(bad\)
[ ]*[a-f0-9]+:[ ]+62 d4 3c 18 8f[ ]+\(bad\)
[ ]*[a-f0-9]+:[ ]+c0[ ]+.*

7
gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
View File

@ -40,3 +40,10 @@ _start:
#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
.insn EVEX.L0.NP.M4.W1 0xff/0, (%rax,%rcx), %rbx
# pop2 %rax, %r8 set EVEX.ND=0.
.insn EVEX.L0.M4.W0 0x8f/0, %rax, %r8
.byte 0xff, 0xff, 0xff
# pop2 %rax, %r8 set EVEX.vvvv = 1111.
.insn EVEX.L0.M4.W0 0x8f, %rax, {rn-sae},%r8
# pop2 %r8, %r8.
.insn EVEX.L0.M4.W0 0x8f/0, %r8,{rn-sae}, %r8

42
gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d
View File

@ -0,0 +1,42 @@
#as: --64
#objdump: -dw -Mintel
#name: i386 APX-push2pop2 insns (Intel disassembly)
#source: x86-64-apx-push2pop2.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx
\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17
\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9
\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31
\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx
\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17
\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9
\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31
\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax
\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8
\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31
\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24
\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax
\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8
\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31
\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24
\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx
\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17
\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9
\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31
\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx
\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17
\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9
\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31
\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax
\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8
\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31
\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24
\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax
\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8
\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31
\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24

13
gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l
View File

@ -0,0 +1,13 @@
.* Assembler messages:
.*:6: Error: operand size mismatch for `push2'
.*:7: Error: operand size mismatch for `push2'
.*:8: Error: 'rsp' register cannot be used for `push2'
.*:9: Error: 'rsp' register cannot be used for `push2'
.*:10: Error: operand size mismatch for `push2p'
.*:11: Error: 'rsp' register cannot be used for `push2p'
.*:12: Error: operand size mismatch for `pop2'
.*:13: Error: 'rsp' register cannot be used for `pop2'
.*:14: Error: 'rsp' register cannot be used for `pop2'
.*:15: Error: two dest registers must be distinct for `pop2'
.*:16: Error: 'rsp' register cannot be used for `pop2p'
.*:17: Error: two dest registers must be distinct for `pop2p'

17
gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s
View File

@ -0,0 +1,17 @@
# Check illegal APX-Push2Pop2 instructions
.allow_index_reg
.text
_start:
push2 %ax, %bx
push2 %eax, %ebx
push2 %rsp, %r17
push2 %r17, %rsp
push2p %eax, %ebx
push2p %rsp, %r17
pop2 %ax, %bx
pop2 %rax, %rsp
pop2 %rsp, %rax
pop2 %r12, %r12
pop2p %rax, %rsp
pop2p %r12, %r12

42
gas/testsuite/gas/i386/x86-64-apx-push2pop2.d
View File

@ -0,0 +1,42 @@
#as: --64
#objdump: -dw
#name: x86_64 APX-push2pop2 insns
#source: x86-64-apx-push2pop2.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax
\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8
\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31
\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24
\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax
\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8
\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31
\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24
\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx
\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17
\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9
\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31
\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx
\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17
\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9
\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31
\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax
\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8
\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31
\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24
\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax
\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8
\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31
\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24
\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx
\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17
\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9
\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31
\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx
\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17
\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9
\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31

39
gas/testsuite/gas/i386/x86-64-apx-push2pop2.s
View File

@ -0,0 +1,39 @@
# Check 64bit APX-Push2Pop2 instructions
.allow_index_reg
.text
_start:
push2 %rbx, %rax
push2 %r17, %r8
push2 %r9, %r31
push2 %r31, %r24
push2p %rbx, %rax
push2p %r17, %r8
push2p %r9, %r31
push2p %r31, %r24
pop2 %rax, %rbx
pop2 %r8, %r17
pop2 %r31, %r9
pop2 %r24, %r31
pop2p %rax, %rbx
pop2p %r8, %r17
pop2p %r31, %r9
pop2p %r24, %r31
.intel_syntax noprefix
push2 rax, rbx
push2 r8, r17
push2 r31, r9
push2 r24, r31
push2p rax, rbx
push2p r8, r17
push2p r31, r9
push2p r24, r31
pop2 rbx, rax
pop2 r17, r8
pop2 r9, r31
pop2 r31, r24
pop2p rbx, rax
pop2p r17, r8
pop2p r9, r31
pop2p r31, r24

3
gas/testsuite/gas/i386/x86-64.exp
View File

@ -345,6 +345,9 @@ run_dump_test "x86-64-avx512dq-rcigrd-intel"
run_dump_test "x86-64-avx512dq-rcigrd"
run_dump_test "x86-64-avx512dq-rcigrne-intel"
run_dump_test "x86-64-avx512dq-rcigrne"
run_dump_test "x86-64-apx-push2pop2"
run_dump_test "x86-64-apx-push2pop2-intel"
run_list_test "x86-64-apx-push2pop2-inval"
run_dump_test "x86-64-avx512dq-rcigru-intel"
run_dump_test "x86-64-avx512dq-rcigru"
run_dump_test "x86-64-avx512dq-rcigrz-intel"

9
opcodes/i386-dis-evex-reg.h
View File

@ -79,6 +79,10 @@
{ "subQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
{ "xorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
},
/* REG_EVEX_MAP4_8F */
{
{ VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) },
},
/* REG_EVEX_MAP4_F6 */
{
{ Bad_Opcode },
@ -102,4 +106,9 @@
{
{ "incQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
{ "decQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) },
},

10
opcodes/i386-dis-evex-w.h
View File

@ -442,6 +442,16 @@
{ Bad_Opcode },
{ "vpshrdw", { XM, Vex, EXx, Ib }, 0 },
},
/* EVEX_W_MAP4_8F_R_0 */
{
{ "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX },
{ "pop2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX },
},
/* EVEX_W_MAP4_FF_R_6 */
{
{ "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
{ "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
},
/* EVEX_W_MAP5_5B_P_0 */
{
{ "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },

2
opcodes/i386-dis-evex.h
View File

@ -1035,7 +1035,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ REG_TABLE (REG_EVEX_MAP4_8F) },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },

31
opcodes/i386-dis.c
View File

@ -105,6 +105,7 @@ static bool FXSAVE_Fixup (instr_info *, int, int);
static bool MOVSXD_Fixup (instr_info *, int, int);
static bool DistinctDest_Fixup (instr_info *, int, int);
static bool PREFETCHI_Fixup (instr_info *, int, int);
static bool PUSH2_POP2_Fixup (instr_info *, int, int);
static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
enum disassembler_style,
@ -900,6 +901,7 @@ enum
REG_EVEX_MAP4_80,
REG_EVEX_MAP4_81,
REG_EVEX_MAP4_83,
REG_EVEX_MAP4_8F,
REG_EVEX_MAP4_F6,
REG_EVEX_MAP4_F7,
REG_EVEX_MAP4_FE,
@ -1739,6 +1741,9 @@ enum
EVEX_W_0F3A70,
EVEX_W_0F3A72,
EVEX_W_MAP4_8F_R_0,
EVEX_W_MAP4_FF_R_6,
EVEX_W_MAP5_5B_P_0,
EVEX_W_MAP5_7A_P_3,
};
@ -13510,6 +13515,9 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
case b_mode:
names = att_names8rex;
break;
case q_mode:
names = att_names64;
break;
case mask_bd_mode:
case mask_mode:
if (reg > 0x7)
@ -13894,3 +13902,26 @@ PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
return OP_M (ins, bytemode, sizeflag);
}
static bool
PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
{
if (ins->modrm.mod != 3)
return true;
unsigned int vvvv_reg = ins->vex.register_specifier
| (!ins->vex.v << 4);
unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
+ (ins->rex2 & REX_B ? 16 : 0);
/* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
|| (!ins->modrm.reg
&& vvvv_reg == rm_reg))
{
oappend (ins, "(bad)");
return true;
}
return OP_VEX (ins, bytemode, sizeflag);
}

3920
opcodes/i386-mnem.h
View File

File diff suppressed because it is too large

9
opcodes/i386-opc.tbl
View File

@ -3480,3 +3480,12 @@ uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
// USER_MSR instructions end.
// APX Push2/Pop2 instructions.
push2, 0xff/6, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
push2p, 0xff/6, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
pop2, 0x8f/0, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
pop2p, 0x8f/0, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
// APX Push2/Pop2 instructions end.

43
opcodes/i386-tbl.h
View File

@ -37287,6 +37287,42 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_push2, 0xff, 2, SPACE_EVEXMAP4, 6,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_push2p, 0xff, 2, SPACE_EVEXMAP4, 6,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 2, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_pop2, 0x8f, 2, SPACE_EVEXMAP4, 0,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_pop2p, 0x8f, 2, SPACE_EVEXMAP4, 0,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 2, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
};
/* i386 opcode sets table. */
@ -37586,7 +37622,8 @@ static const i386_op_off_t i386_op_sets[] =
3842, 3843, 3844, 3845, 3846, 3847, 3848, 3849,
3850, 3851, 3852, 3853, 3854, 3855, 3856, 3857,
3858, 3859, 3860, 3861, 3862, 3863, 3865, 3867,
3869, 3871, 3873, 3874, 3875, 3877, 3879
3869, 3871, 3873, 3874, 3875, 3877, 3879, 3880,
3881, 3882, 3883
};
/* i386 mnemonics table. */
@ -37624,7 +37661,9 @@ const char i386_mnemonics[] =
"\0""vsha512msg2"
"\0""vsm3msg2"
"\0""sha256msg2"
"\0""push2"
"\0""fldln2"
"\0""pop2"
"\0""vsha512rnds2"
"\0""vsm3rnds2"
"\0""sha256rnds2"
@ -38714,6 +38753,8 @@ const char i386_mnemonics[] =
"\0""cqto"
"\0""ssto"
"\0""cmovo"
"\0""push2p"
"\0""pop2p"
"\0""bswap"
"\0""fsubp"
"\0""pfrcp"

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