riscv
/
binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

gas/ 

2013-04-09  Jan Beulich <jbeulich@suse.com>

	* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
	if there was none specified for moves between scalar and core
	register.

gas/testsuite/
2013-04-09  Jan Beulich <jbeulich@suse.com>

	* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
	* gas/arm/neon-omit.d: Update accordingly.
cygwin-64bit-premerge-branch
Jan Beulich 14 years ago
parent
2d51fb7431
commit
05ac0ffbb5
5 changed files with 38 additions and 0 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 6
      gas/ChangeLog
  2. 20
      gas/config/tc-arm.c
  3. 5
      gas/testsuite/ChangeLog
  4. 2
      gas/testsuite/gas/arm/neon-omit.d
  5. 5
      gas/testsuite/gas/arm/neon-omit.s

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
if there was none specified for moves between scalar and core
register.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the

20
gas/config/tc-arm.c
View File

@ -15360,6 +15360,16 @@ do_neon_mov (void)
unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
/* .<size> is optional here, defaulting to .32. */
if (inst.vectype.elems == 0
&& inst.operands[0].vectype.type == NT_invtype
&& inst.operands[1].vectype.type == NT_invtype)
{
inst.vectype.el[0].type = NT_untyped;
inst.vectype.el[0].size = 32;
inst.vectype.elems = 1;
}
et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
logsize = neon_logbits (et.size);
@ -15409,6 +15419,16 @@ do_neon_mov (void)
unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
unsigned abcdebits = 0;
/* .<dt> is optional here, defaulting to .32. */
if (inst.vectype.elems == 0
&& inst.operands[0].vectype.type == NT_invtype
&& inst.operands[1].vectype.type == NT_invtype)
{
inst.vectype.el[0].type = NT_untyped;
inst.vectype.el[0].size = 32;
inst.vectype.elems = 1;
}
et = neon_check_type (2, NS_NULL,
N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
logsize = neon_logbits (et.size);

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
* gas/arm/neon-omit.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for further invalid VST

2
gas/testsuite/gas/arm/neon-omit.d
View File

@ -93,4 +93,6 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3954556 vsli\.16 q2, q3, #5
0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63.*
0[0-9a-f]+ <[^>]+> f2b25386 vext\.8 d5, d18, d6, #3
0[0-9a-f]+ <[^>]+> ee000b10 vmov(\.32)? d0\[0\], r0
0[0-9a-f]+ <[^>]+> ee100b10 vmov(\.32)? r0, d0\[0\]
0[0-9a-f]+ <[^>]+> f3020d54 vmul\.f32 q0, q1, q2

5
gas/testsuite/gas/arm/neon-omit.s
View File

@ -96,5 +96,10 @@
vqshlu.s64 d15,d23,#63
vext.8 d5,d18,d6,#3
@ Also test VMOV with omitted suffix:
vmov d0[0], r0
vmov r0, d0[0]
@ PR 11136 - this used to crash the assembler.
vmul.f32 q0,q1,q2

Write Preview
Loading…
Cancel
Save