RISC-V: Add T-Head Int vendor extension

This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

bfd/elfxx-riscv.c

@@ -1240,6 +1240,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadcondmov",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadfmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadfmv",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadint",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmempair",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2422,6 +2423,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadfmemidx");
     case INSN_CLASS_XTHEADFMV:
       return riscv_subset_supports (rps, "xtheadfmv");
+    case INSN_CLASS_XTHEADINT:
+      return riscv_subset_supports (rps, "xtheadint");
     case INSN_CLASS_XTHEADMAC:
       return riscv_subset_supports (rps, "xtheadmac");
     case INSN_CLASS_XTHEADMEMIDX:
@@ -2578,6 +2581,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadfmemidx";
     case INSN_CLASS_XTHEADFMV:
       return "xtheadfmv";
+    case INSN_CLASS_XTHEADINT:
+      return "xtheadint";
     case INSN_CLASS_XTHEADMAC:
       return "xtheadmac";
     case INSN_CLASS_XTHEADMEMIDX:

gas/NEWS

@@ -26,7 +26,7 @@
   for --enable-compressed-debug-sections.
 
 * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs,
-  XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx,
+  XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadInt, XTheadMemIdx,
   XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head
   ISA manual, which are implemented in the Allwinner D1.
 

gas/doc/c-riscv.texi

@@ -739,6 +739,11 @@ The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precisi
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
 
+@item XTheadInt
+The XTheadInt extension provides access to ISR stack management instructions.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
+
 @item XTheadMac
 The XTheadMac extension provides multiply-accumulate instructions.
 

gas/testsuite/gas/riscv/x-thead-int.d

@@ -0,0 +1,11 @@
+#as: -march=rv32i_xtheadint
+#source: x-thead-int.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0040000b[ 	]+th.ipush
+[ 	]+[0-9a-f]+:[ 	]+0050000b[ 	]+th.ipop

gas/testsuite/gas/riscv/x-thead-int.s

@@ -0,0 +1,3 @@
+target:
+	th.ipush
+	th.ipop

include/opcode/riscv-opc.h

@@ -2213,6 +2213,11 @@
 #define MASK_TH_FMV_HW_X 0xfff0707f
 #define MATCH_TH_FMV_X_HW 0x5000100b
 #define MASK_TH_FMV_X_HW 0xfff0707f
+/* Vendor-specific (T-Head) XTheadInt instructions. */
+#define MATCH_TH_IPOP 0x0050000b
+#define MASK_TH_IPOP 0xffffffff
+#define MATCH_TH_IPUSH 0x0040000b
+#define MASK_TH_IPUSH 0xffffffff
 /* Vendor-specific (T-Head) XTheadMac instructions.  */
 #define MATCH_TH_MULA 0x2000100b
 #define MASK_TH_MULA 0xfe00707f
@@ -3130,6 +3135,9 @@ DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW)
 /* Vendor-specific (T-Head) XTheadFmv instructions. */
 DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X)
 DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW)
+/* Vendor-specific (T-Head) XTheadInt instructions. */
+DECLARE_INSN(th_ipop, MATCH_TH_IPOP, MASK_TH_IPOP)
+DECLARE_INSN(th_ipush, MATCH_TH_IPUSH, MASK_TH_IPUSH)
 /* Vendor-specific (T-Head) XTheadMac instructions.  */
 DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
 DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)

include/opcode/riscv.h

@@ -417,6 +417,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADCONDMOV,
   INSN_CLASS_XTHEADFMEMIDX,
   INSN_CLASS_XTHEADFMV,
+  INSN_CLASS_XTHEADINT,
   INSN_CLASS_XTHEADMAC,
   INSN_CLASS_XTHEADMEMIDX,
   INSN_CLASS_XTHEADMEMPAIR,

opcodes/riscv-opc.c

@@ -1935,6 +1935,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X,  MASK_TH_FMV_HW_X,  match_opcode, 0},
 {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW,  MASK_TH_FMV_X_HW,  match_opcode, 0},
 
+/* Vendor-specific (T-Head) XTheadInt instructions.  */
+{"th.ipop",  0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP,  MASK_TH_IPOP,  match_opcode, 0},
+{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadMemIdx instructions.  */
 {"th.ldia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA,  MASK_TH_LDIA,  match_th_load_inc, 0},
 {"th.ldib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB,  MASK_TH_LDIB,  match_th_load_inc, 0},